ASIC designers are finding that custom SoCs in 90nm or 65nm technologies will cost more to develop than those for earlier process nodes. Just how expensive is a matter for debate. One thing for sure is that a platform-based system design approach can dramatically reduce the development time and risk of complex SoCs, and that translates to lower development costs and faster time-to-market.

Platform-based system design is like standing on the shoulders of those who came before you. Anyone who has ever designed a system with an off-the-shelf ASSP has done a platform-based design. That ASSP was the result of many man-years of effort, but by using it you could launch your product in a matter of months. Likewise, anyone who has ever written a program to run on a Windows or Linux platform has benefited from not having to design the hardware and OS themselves. You take what's already working and customize it to your needs.

So why should we read about platform-based system design on SoCCentral? What's new or at least a hot topic at the moment is the perceived rising cost and development time of nanometer-scale SoCs (90nm and smaller).

Many companies have built their fortunes on products that would not have been possible without customized silicon (ASICs), but even the boldest risk-takers among us have to stop and think before committing to a 2.5-year, $10M, 90nm custom SoC development project. Especially when you consider that you could buy a lot of $45 FPGAs and $20 ASSPs for $10M and have your ASSP/FPGA-based product on the market in 6 months.

But what if the custom 90nm SoC development cost was only $4M, and you could reduce your BOM cost by $40 by replacing an ASSP/FPGA combo with a highly optimized single-chip solution? Then the development would pay for itself after only 100,000 units. What if the 2 to 3 year design cycle was reduced to only 6 months and you could be sure the first silicon worked? Best of all, what if you could have your product in the market 10 to 12 months after project start and know that it is better than your competitors' because of something clever you put in the silicon? It is these kinds of results that make platform-based design exciting when applied to SoCs.

So, how does it work?

A platform-based SoC design methodology starts with the equivalent of a Linux workstation that can be dropped into a customer's ASIC. It's actually a soft IP-core-based computing and I/O platform that the customer can use as a starting point for their design, then simply add their own custom logic, much like making a PCI plug-in card for a PC. Add to this pre-existing ports of Linux and other embedded OSs, and the customer's software job just got a lot easier -- simply add a driver for their own logic and then run their application. The key here is that most of the SoC and system software design is already done before the customer even starts the project, reducing development time.

Cell-Based Platform SoC System Architecture

Another benefit of a platform-based design approach is reduced risk, in particular the risk of a respin. In nanoscale designs, each mask set is expensive relative to today's more conventional ASICs. Also, nanoscale designs can take longer to lay out, which makes it more expensive to tape out. So mistakes really cost you in terms of ASIC NRE or the much more serious 6 to 9 month schedule slip, which could push your product right out of the market. Yes indeed, respins are expensive. Platform-based designs greatly reduce the risk of respins, especially if co-development models of the SoCs are available. The customer can actually run their code on a model of the SoC before it tapes out. The chances of first-time silicon success are very high.

One more point I'd like to make about software: even if your SoC is working, you don't have a product to sell until the software is working. A platform-based design methodology that incorporates HW/SW co-development means you can develop your software before you have silicon, which considerably shortens the software schedule. HW/SW co-development has been an underutilized technology because it can be complicated to deploy. A real benefit of platform-based design is that the hard part of the HW/SW modeling is already done, allowing the software team to work closely with the SoC team during SoC development. The end result is much faster end-product development cycles.

I've mentioned custom SoC development costs of $4M as though this were a mere drop in a bucket. I don't want to leave the wrong impression here: the $4M figure is for a complex and highly optimized 90nm IC that is ahead of the curve. For more middle-of-the-road needs (and we're talking 3-4M gates, which is enough for many applications), a custom SoC can cost much less. There has never been a better time to make an ASIC. If you can meet your goals with 180nm or 130nm technology, prices are competitive, EDA tools work really well, and there are many experienced ASIC vendors you can rely on. When you are ready to move to 90nm, 65nm or 45nm, it will turn out that today's concerns about cost and risk have been resolved by custom SoC vendors like Toshiba who are already using the latest platform-based design methodologies to develop complex, nanoscale SoCs.

By Steve Williams, SoC Business Development, Toshiba America Electronic Components, Inc.