May 6, 2005 -- Structured ASIC platforms have come a long way since their introduction three years ago. Originally conceived as a bridge between design approaches using quick-but- expensive FPGAs or full standard cell ASICs, they have offered users access to the latest semiconductor technology with reduced risks and costs, and more rapid time to market. As they've evolved, the structured, or platform ASIC, design approach has proven effective in reducing NREs by as much as 60 to 70 percent, and minimizing the impact on engineering resources.
And now the technology is advancing. One major move forward has been support in new versions for various high-speed serial interfaces at data rates from 622 Megabits/second all the way to 3.125 Gigabits/second, and even higher. A broad range of telecom and networking interfaces also has been made available now, with PHY technology that includes an area of logic that completes physical layer functionality, allows users to program the PHY as required at the metallization stage.
Dedicated DDR blocks, for example, address the common problem of timing closure across external interfaces to high-speed memories, or from chip-to-chip. The DDR blocks create the flexible adjustment to timing of the external signals. Also, around the edge of each structured ASIC device now are single-port RAMs which are used as register files of FIFOs. The 16-block I/O area supports various types ranging from LVCMOS to PCML, and can be implemented by the designer at the metallization stage.
Another important advance in the structured or platform ASIC has been the integration of serialization-deserialization (SerDes) technology have set a performance record for applications requiring wide bandwidth. By 2007, many custom designs will use SerDes technology to increase system bandwidth, relieving I/O bottlenecks by compressing slower-speed parallel data in much faster serial data. It also has the effect of reducing total system costs. So integrating SerDes cores into structured ASIC platform is an excellent strategy. But, it is not trivial, requiring expertise and experience in a field-proven platform.
Figure 1. Integrating SerDes blocks increases system bandwidth, reduces the pin counts necessary to support a given data bandwidth, and reduces overall design and ASIC costs.
In a networking application, the serializer in the SerDes block converts 400 MHz parallel data coming from inside the network card to 3.125 Gbps serial data as output to the backplane bus. The deserializer in another SerDes block then retrieves the data from the backplane bus, converting it back to slower parallel data. By implementing these techniques, the net traffic flowing across the line-card-to-backplane interface is increased by a factor of at least two times, and up to four times that of the incoming data rate.
Utilizing SerDes technology also results in reduced pin counts needed to carry a given data bandwidth. In the case of 16-bit parallel data, the pin count reduction is factor of 16. The result is that by implementing SerDes technology, it is possible to increase the maximum data bandwidth through the available connector pins at the backplane interface.
Integrated SerDes also has the salutary effects of lowering system-level power consumption to minimums, and reducing design and ASIC cost, because the need for external components and parallel wires are needed to route at the board level is reduced.
Choosing the Vendor
The choice of structured or platform ASIC vendors has grown as the technology has evolved. There are several important criteria on the 'check off' list for user when selecting the platform ASIC vendor. Start with the general history and success of the company in the ASIC market, of course. While past performance is no guarantee, it is a guidepost. The platform ASIC vendor must have the knowledge and expertise to analyze signal integrity and other system design issues to ensure a low risk and first time success design. The level of integration is another key consideration for optimum selection.
The platform's viability rests in large part on the number of available gates and other on-chip resources. Potential users should examine the structured ASIC's logic architecture to determine the granularity of base logic cells and, as a result, the flexibility that is available when implementing a circuit. Also, when selecting a chip from a family, make sure the platform includes room for expansion, which enables the addition of features later.
Other important resources include on-chip clock support and distribution, particularly vital for implementing high-performance designs, which generally utilize multiple clock domains. Some of these can run from the same master clock, while some require independent clock sources. When examining the on-chip resources, evaluate the number and types of phase-locked loops, delay-locked loops, clock buffers, and predefined clock trees that are available. Also check the vendor's intellectual-property library and third-party support for additional timing support functions. Most of the leaders in structured and platform ASICs are well-equipped now, but check anyway.
For communications and networking applications, there are specific considerations, such as SerDes specifications including low jitter performance, low power, and noise resistance. An example: silicon with 64-ch of 3.125G SerDes. The embedded SerDes must enable the ASIC to tolerate the losses associated with multi-gigabit traffic over printed circuit board traces and XAUI system Backplane circuit boards and Backplane connectors.
AccelArray Platform: Giga Platforms
One of the newest selections available is Fujitsu's GigaFrame platform, a fully proven technology with 16 and 24-channels of embedded SerDes operating up to 3.125Gbps with total aggregated BW of up to 150Gbps full duplex. The platforms utilize a universal SerDes solution that supports multiple standards such as XAUI, PCI express and serial Rapid I/O and Fibre Channel.
The platforms support up to 3Mb of true dual port SRAMs with over 5 million raw logic gates. The AccelArray technology offers a proven, fully verified and tested platform with integrated SerDes functionality that drastically reduces the ASIC pin count, leading to smaller and lower-cost chips.
And the value proposition for structured/platform ASIC technology continues to evolve as companies work together to maximize its potential for customers. Late last year, Fujitsu Limited, Fujitsu Microelectronics America, Inc. (FMA) and Synplicity, Inc., a leading supplier of software for the design, announced a joint development agreement to develop a custom physical synthesis product for Fujitsu AccelArray ASIC devices. Fujitsu and Synplicity are working closely to produce an optimized version of Synplicity's Amplify physical synthesis software, specifically targeting the AccelArray architecture and enabling greater performance and faster overall timing closure for Fujitsu's devices. The result: one of the industry's most compelling structured ASIC values is getting even better.
By Simone Shaghafi, Fujitsu Microelectronics America
Go to the Fujitsu Semiconductor America, Inc. website to learn more.