June 1, 2005 -- For "DAC month," SOCcentral Contributing Editor Jim Lipman cornered Raul Camposano, Synopsys' Chief Technology Officer and General Manager of the Silicon Engineering Group, to get his opinion on upcoming EDA challenges and some important issues affecting chip design over the next few years.

Lipman: What are the major technical challenges for EDA vendors developing tools for 65nm and beyond?

Camposano: That's an excellent question. The way we look at the world is, essentially, we see four main areas. Tools have always addressed implementation and verification. Implementation is based on synthesis, placement and routing, but also includes things like static timing analysis and power analysis. In verification, the traditional way to do it was simulation. You now add to that all the formal and semi-formal techniques from testbenches to property checking, equivalence checking, and so on.

"Core EDA" continues to be a technical challenge, essentially because the chips are growing larger and larger and the systems are becoming more and more complex. Every generation brings an additional amount of complexity. In addition to the complexity, the core areas of EDA are becoming more complicated because fabrication issues - we used to call them deep-submicron issues - are creeping in, particularly in physical design. You still have to take into account some things we have done for awhile, but now you must consider additional things like yield, printability, lithography, cracking, and CMP to be able to do effective physical design. That's a big challenge that's making implementation more important.

In addition to these two areas - implementation and verification - we have been, of course, moving up into the system level. There, our main area has been IP; we think that this is really the method that scales. For IP, the bigger your IP blocks, the simpler your design becomes. IP is used to build platforms. If you have a processor with all of its peripherals, DSP, and certain types of memory, it's very easy to build a platform very quickly by adding, maybe, a little bit of your own design. IP is the key to system-level design. Then, of course, if you go one level further you have software. With software, the name of the game is standardization for platforms and what you need to do to be able to reuse your software and build platforms for applications such as cell phones.

The other big challenge, moving down towards the process, is what EDA is calling DFM - design for manufacturability - which, for us, encompasses three things. You have to do it in design and I already talked a little bit about that. That's DFM, per se - what can you do in design to make a design more manufacturable, to yield more. It's mainly physical design, but not only that. Then, you have to do it during lithography. Once you have GDS-II, the output of the physical design (you don't have the mask yet), you have to add assist features and do OPC [optical pattern correction] and RET [reticle enhancement technology] in general, maybe PSM [phase-shift masks] and fracturing. Hence, there is lithography simulation and a lot of additional steps that you do before you actually get to the masks associated with lithography. A lot can happen there and we are, of course, a big player in that market. All that is getting increasingly more complicated because you have to do more correction. You have to do it on more layers, but you also have to do more correction on each layer as we go further into sub-wavelength lithography.

The third part that you do for DFM is in manufacturing. That's been the area where, traditionally, just the fabs and equipment manufacturers played, but we're getting involved, particularly because a lot of the things can now be simulated, so TCAD is a particularly interesting area. We can simulate processes and devices, all the way to extracting, in a simulator, electrical parameters that can show process manufacturing issues actually affecting electrical parameters and, ultimately, the exact parameters of a design.

Lipman: You touched on a lot of things. One thing I would like to elaborate on - you discussed the fab with the third part of DFM. I know you have a very close working relationship with TSMC with its Reference Design Flow. How is this working out between you and TSMC and how does it benefit the ultimate customer?

Camposano: That's a key point. I think that if you look at foundries and the fabless model in general where you don't have an integrated company, an IDM that is doing everything, it's very important to have an interface that is very clear between the designer and the actual foundry. To get this reference flow defined clearly for a particular process is something that's of great benefit for the customer, on one hand, but also for the foundry because it will get designs that will yield much quicker and will work sooner. So, it's working out fine and I think that it's an integral part of the fabless model that has enabled so much growth.

Lipman: What areas of chip design do you feel are going to need the most EDA effort to meet the evolving cost/performance tradeoffs that we see happening? System design and analysis, DFM, power reduction, or something else?

Camposano: I think that one needs to start at the bottom, close to the process. If you look at the investments that are happening and at the EDA revenues, taking a systematic view of things, the area that has grown the most in the last five years is very clearly DFM and things that are associated very closely to the lithography of the process, because it's getting so difficult. That's just going to get more and more difficult with every process node, so there's tremendous growth there. I think it's fair to say that it's one of the largest challenges because this is where a large part of the investment growth goes.

Having said that, I don't want to minimize what happens for all the rest. There's great hope that DFM, for example, will enable a designer to an even larger extent than it does today to do designs quicker, to get higher yield, and to do things in design, in particular for very high-volume designs, that can be corrected in some kind of loop. However, as I mentioned, most of the actual investment growth and the effort have gone, in the last few years, into DFM. This is the area that has seen the largest growth and I expect that to continue for awhile.

Lipman: Some articles lately have indicated that chip vendors, particularly the IDMs, are developing more in-house EDA tools because they feel they can't get what they need for their leading-edge designs from the traditional EDA-tool vendors. Do you have any comments on this?

Camposano: I think that this has been a very long-standing issue. I worked at IBM in the 1980s. IBM had a large EDA group in those days and they still have an EDA group today. Obviously, all the large IDMs have internal EDA groups that work on problems. I don't think that this is anything new. I think that if you just look at the economics of designs, as they get more and more complicated, the economy of scale of being able to use software where, ultimately, the development cost is shared across the industry, is something that's going to become more important.

If you look at what's happening in the fab domain, you see that today you have groups that develop fabs together. You have the Crolles Alliance in Europe, where Motorola [now Freescale], ST and Philips are working together. IBM has a group of partners around them doing pre-competitive development. If anything, the bar and cost are rising. If you can leverage what an EDA vendor can do and it can be used by a large number of designers, mask houses and fabs, that's the way to go.

Having said that, there are always instances where there is a competitive advantage a large company may think they have by developing a tool, and that's going to continue to happen. To give an example, a very large amount of design is cell-based. There are instances of very high-performance design where people have specific methodologies of doing transistor-level design for which you may not be able to find commercial tools, so you develop some software around those specific methodologies. But, anything that's mainstream or is used by large numbers of people will not be done that way.

Lipman: I know that Synopsys is very heavily involved in the development of open standards for the EDA industry. What areas of chip design do you feel would benefit most from more development and widespread acceptance of tool and interface standards?

Camposano: My first observation would be that I think that the state of the art here is probably a little bit more evolved than the industry gets credit for. There are a lot of standards that have been out there for a very long time and are accepted to exchange information between tools. These include things like GDS-II, OASIS, LEF and DEF, Verilog, VHDL, netlist standards, and so on. These tend to be text formats and allow you to interchange designs at a certain level of granularity. Of course, I'm sure that you're thinking of things like OpenAccess and open databases.

One of the promises that people associate with this is to be able to work on a design at a very fine level of granularity so you don't have to read and write a complete module or complete design. You can incrementally go in and change some things if you have the design represented in these databases. I think the natural progression is to go from text formats, maybe, to binary formats, which are a little bit more efficient. Then we'll get into some level of granularity beyond what we can today. I think that OASIS has offered tremendous progress in the sense that the data volume is so big that having more compact formats has helped a lot.

If you look at those applications that would benefit with something like OpenAccess, where a database is very important, they are, to a large extent, in analog design. You have a closed loop - you need your schematics, layout, simulator, extraction and design-rule check to all be tied in a very closed loop. If you look at digital designs, which tend to be much, much bigger, then the loop isn't as tight. The advantage of having a more interactive database is not that big there. In analog and I/Os, things that require a very tight loop, you can see more of an advantage.

Lipman: I know there are a lot of organizations that work with these exchange and interface standards. Can you name two or three that you think are doing a better job than average, with whom you work with more?

Camposano: I think that at the end of the day, IEEE standards are what everyone aspires to when things are really mature, and that's good. Among others we work with is Accellera in terms of standardizing SystemVerilog. I think there is going to be a big push to that standard, not just raising Verilog to SystemVerilog but also the testbench standards and assertion standards that come with it.

Lipman: We've covered a lot of ground and this is very good information. One more question - where do you think Synopsys will make the biggest contribution to chip design in the next five years?

Camposano: We are mainly in IC design, almost exclusively in IC design. That's where we'll continue to work. Within IC design, we have a comprehensive tool offering that covers all the areas. Just to summarize, for us this covers four areas: IP at system-level design, which is key; implementation; verification; and DFM, design for manufacturability. I think that one of the areas in which we are putting a little more emphasis, besides DFM, is the analog area. We recently closed the acquisition of Nassda, giving us another piece of fast Spice simulation, which is very important for analog. This is something that we'll put more emphasis on over the next few years.

Lipman: Thanks for giving SOCcentral the opportunity to present your views.

Dr. Raul Camposano joined Synopsys in 1994 and currently serves as Chief Technology Officer and Senior Vice President. His responsibilities include the Advanced Technology Group and IT, EIS and SW Engineering. He previously served as General Manager of all Synopsys Design Tools business units and was also Vice President of Engineering. Elected an IEEE Fellow in 1999, he serves on technical program committees and editorial boards worldwide and has published over 70 articles and three books on EDA. Dr. Camposano holds a B.S. and an M.S. in E.E. from the University of Chile, and a Ph.D. in Computer Science from the University of Karlsruhe.