November 15, 2005 -- Of course, there is a difference between logic synthesis and physical synthesis. Typically, the former maps an RTL description to a set of gates to realize the same functionality. Conversely, the latter implements the netlist on a given (minimal) floorplan and maintains or improves the quality of physical characteristics of the design. These characteristics could include timing, power, testability, signal integrity, routability and manufacturability, all leading to improved yield for the device.

Looking through the reality viewfinder, however, shows a much different perspective for many design project teams. For example, logic synthesis is a disparate step, performed in almost complete isolation. The logic design engineer writes (or receives) functionally verified RTL code and begins to synthesize it with incomplete timing constraints. Whether the concept of wireload is used for selecting the most optimal cells, traditional methods ignore a design’s physical requirements. This leads to a false sense of "timing closure" too early in the design process and a false sense of confidence that the logical netlist can be implemented by the physical design team.

All too often, the physical design team struggles to meet timing, area, power, testability and signal integrity goals – collectively known as design closure. The never-ending iterations are usually caused by the incomplete constraints, a poor RTL coding style or lack of any planning for cell placement. All of which suggests that a better, more predictable flow is necessary.

Historically, physical synthesis came about when the designs were small, slow and simple by today’s standards. Designing a few hundred thousand gates at hundred MHz at 0.25 micron may have been challenging at that time. Today, it is merely considered an undergraduate-level, semester class project.

The separate logic and physical synthesis of yesterday is no longer appropriate for today’s multi-million gates, gigahertz SoC designs in nanometer processes. From the outset, designers must understand and optimize with the goal of achieving design closure. Further, timing, area, power and testability are not individual goals that can be achieved in isolation.

Consider this: For a design with 100 adders, the logic designer was able to meet timing after logic synthesis and all adders were Ripple Carry adders to give the smallest area. When the physical designer attempts to place the netlist, some long blockages due to shapes of RAMs, ROMs or other hard macros make a physical path too long and the first timing closure problems become apparent. After a struggle, it becomes obvious that an adder must be faster in order to achieve the required timing. The notion of an adder was lost when the netlist was supplied to physical synthesis tool. The netlist goes back to the logic designer who must resynthesize the RTL, adding some timing constraints.

An attempt is made to place the new netlist, and the previously failing path may not even be placed around the long blockages. Another path, perhaps with another Ripple Carry adder, fails.

And, that is the point – there is no predictable means during logic synthesis to determine which adders (or any datapath logic) must be swapped for a faster architecture with the same functionality. This causes multiple iterations, wasted time and effort and, eventually, poor quality of results. Changing all datapath components to the fastest available architecture is not a wise solution because it increases the cost in area and power. The same applies when the netlist requires manipulation for managing power, testability, routability or manufacturability. Re-structuring the netlist as a post-processing step means endless iterations and an eventual disaster.

While the concept of RTL to placed gates or a physical netlist is not new, it has become much more important as complexity increases through the multiple dimensions of leading-edge SoC designs. Design tools providing RTL-to-placed gates flow must have features beyond traditional point tools.

First, is high capacity for large flat synthesis. Managing multi-million gates chips is beyond the capabilities of legacy tools. Dividing logic into a few hundred thousand gates requires integration of 25 to 50 blocks at the top level and managing multiple levels of hierarchy. When such logical partitions are created, the mapping to physical partitions becomes an enormous task.

Closing timing on lower-level blocks is no guarantee that timing closure, not to mention design closure, can be achieved at the chip level. Newer tools, built for sub-100 nanometer processes, have much larger capacity to handle four- or five-million gate designs without having to partition it.

Next, is early predictability. In addition to the capacity of the synthesis tool, it is important to achieve early visibility into problems that can occur later in the physical design, which will help avoid iterations later in the design process. This predictability can be achieved only when logic synthesis and physical synthesis are integrated and share the same data for making netlist changes.

Next, is addressing power optimization throughout the placed gates flow and beyond. Low power has become the necessity for all portable and wireless consumer devices. Integration of logic and physical synthesis permits power management options from architecture and clock gating to various library cell selections and power grid. A design that has a smaller cell count will also result in lower power.

Finally, the flow must be flexible to accommodate different business relationships between the front-end designer and the physical designer. Whether the project team is pursuing a COT flow or an ASIC flow, whether the teams are geographically dispersed or in the same time zone, the hand-off between teams should be based on the complexity of the design and the skill set of available team members.

If the system architect wants to enforce certain clocking schemes or a power-grid structure prior to design closure by the front-end team, he or she should be allowed to carry out the flow deeper in the physical domain. At the same time, the hand-off can be functionally verified RTL and a set of timing constraints so the physical team can make use of a fully integrated RTL-to-GDSII flow without a single break. Many design managers now refer to this as hand-off region or hand-off zone rather than a hand-off point.

Logic synthesis and physical synthesis should not be separated because every front-end designer has a certain amount of physical design knowledge. It’s only when design closure is achieved at the placed gates stage should the front-end designer consider handing it to the physical designer.

By Yatin Trivedi, Director of Product Marketing, Magma Design Automation, Inc.