March 6, 2006 -- Verification troubles have been the talk of the town for the last five years, but the underlying cause has had less attention recently. Specifically, verification is becoming more difficult because the chips have more functions, more gates, more complexity. Transaction level modeling (TLM) arose as a technique to address the verification challenges; TLM was all about verification and not at all about design implementation - until now.
Transaction level models provide an abstraction layer above RTL which leads to significant simulation performance advantages. SystemC now supports TLM modeling, and is well-suited for this type of higher level abstraction, in contrast with RTL languages like Verilog or its derivatives. By abstracting interface details such as specific bit-level data and timing using a “transaction” to carry all of the necessary information in one quick burst, there are fewer simulation events leading to better simulation performance. The TLM allows all the necessary data to flow between modules without the need to simulate the mundane input/output timing. These faster models can then be used for functional verification, firmware integration, software bring-up, etc. However, until recently, the TLM model typically was not an implementation model and became unlinked from the design process, leading to separate design and verification models.
A methodology and toolset which allows one golden model for both design and verification is desirable because it reduces the risk of managing multiple out-of-sync versions of the design. Designers can create a high-level algorithmic or behavioral model with transaction level interfaces for early validation of the functionality and software integration. These models typically run between 100x and 1000x faster than RTL simulation. Then, using a product such as Forte Design Systems’ Cynthesizer ESL synthesis product, the TLM design can then be automatically ‘cynthesized’ to create high-quality RTL implementation models with the desired I/O interfaces replacing the TLM interfaces according to specified area, performance, and power tradeoffs. Additionally, each interface can easily and quickly be re-specified and replaced without causing changes to the TLM design. Try that in RTL.
Transaction level modeling is part of the greater move to the Electronic System Level or ESL. This drive to handle more complex devices has pushed the industry to develop a methodology and toolset for better design and verification – more gates, less time, and to integration with an alien being – software! Products exist today that can produce better designs, in less time, and reduce the risk inherent in design and verification. These tools are in production use all over the world, including the US. The move to ESL from RTL will closely resemble the move from schematics to RTL and the leaders have already started.
By Brett Cline, Vice President, Customer Operations & Services, Forte Design Systems, Inc.
Brett Cline joined the Forte team in 1999 and served as Vice President of Marketing from 2002 until 2005 where he drove the product direction and customer introduction of Forte’s Cynthesizer. He is currently responsible for Forte’s consulting and support services delivering key account customer success. Before joining Forte, Cline was Director of Marketing at Summit Design, where he managed both the verification product line and marketing communications; He holds a BSEE from Northeastern University in Boston, Massachusetts and serves as an advisor to several EDA startups.
Go to the Forte Design Systems, Inc. website to learn more.