June 16, 2006 -- In Part 1 of this piece, we first described just what Structured ASICs are, and we then posed the question: "If Structured ASICs are so wonderful, why aren’t more people using them?"
Actually, that really wasn't very fair of us (shame on you). In reality, quite a few folks are using Structured ASICs, but it's probably fair to say that this market hasn’t grown as fast as many industry observers expected and predicted. Also, different folks are using Structured ASICs for different reasons, and it can be somewhat tricky to wrap your brain around all of this if you're not careful. So let's consider some of the players and try to work out what they're doing and – possibly – why they're doing what they're doing (As Captain James T. Kirk might say: "Let's boldly go behind the beyond, behind which few men have boldly gone behind, beyond, before!").
Personally I always think a diagram helps, so take a moment to glance at Figure 4 (this may not be comprehensive, or even particularly accurate, but – if nothing else – it adds a splash of color, so that's OK).
Figure 4. The Structured ASIC universe
What? Yes, I know it's not pretty, but that's the way it goes sometimes (if you have a better way of representing this morass of confusion I'd love to see it).
Now, before we start, it's important to remember that I'm making all of this up as we go along. The following does not represent the views of any of the companies involved; this is just my take on things and other folks may have a very different perspective.
Let's start with the big fabs who have their own Structured ASIC offerings. The two that leap to mind are Fujitsu and NEC (LSI Logic used to sort-of fit into this group with its "Platform ASICs" before it bailed out of the market earlier this year). Apart from the fact that LSI liked selling lots and lots of silicon chips, there's a big advantage in producing Structured ASICs for these folks. In the not-so-distant past, when a new silicon chip technology node came online, the process was ironed out using memory chips. For example, when the 2.5-micron node first made an appearance deep in the mists of time, the first devices that were made available using this node were memory chips; general-purpose logic devices tended to follow a year or so later once all of the kinks had been worked out of the process.
One of the reasons memory chips were useful in this regard is that they have a regular, repeated, highly characterized structure. More recently, fabs have used FPGAs to prove a new technology node; for example, I understand that Xilinx FPGAs were used by several fabs while establishing their 90-nm and 65-nm nodes.
The bottom line is that if you're a fab and you're bringing a new technology node online, you dream of having a requirement to produce a large number of identical wafers, especially if they contain lots and lots of copies of the same logic. And, of course, the point is that Structured ASICs are based on a regular, repeated, highly characterized structure. Thus, quite apart from the fact that they enjoy selling Structured ASICs in their own right, Toshiba and NEC can also use their Structured ASIC offerings as "pipe cleaners" to clean out a new process and get a new technology node up and running as fast as possible.
Another big market for Structured ASICs is FPGA-to-ASIC conversion. Let's suppose that you create a new product but initially you don’t expect to sell more than a few thousand. In this case, you might start with an FPGA. If at some stage your product starts to go "gang-busters" and looks like it's going to sell in quantities of many tens of thousands, you're going to want to convert your design into some form of ASIC, because these will be much cheaper (in terms of cost-per-chip) in large quantities, plus they have the advantages of higher performance and lower power consumption. Another scenario is to quickly prototype a design using an FPGA to get early versions out into the field so that other folks like embedded software developers can start performing their magic. Once you've received feedback, you have implemented any necessary modifications to your design, and you're happy that all is as it should be, you may wish to migrate the design into some form of ASIC for mass production.
As we've already noted, however, designing a conventional ASIC from the ground up is horrendously expensive and time-consuming, so you only want to go this route if you plan on selling hundreds-of-thousands or millions of the little scamps. This opens the door to Structured ASIC implementations. As a rule of thumb, if you intend to produce only a few thousand units, then an FPGA is the way to go; if you're planning large-scale production of 500,000 units or more, then a full-blown ASIC will give you the best bang for your buck; but if you're anticipating a mid-range production run of around 50,000 units, then a Structured ASIC may be the best option (especially when you take into account the fact that the overall development time for a Structured ASIC can be much shorter than for a full-blown ASIC). (As usual, don’t forget that these numbers are just some that I pulled out of the air – in reality, there will be gray areas depending on a range of considerations such as the size and complexity of the design.)
The only FPGA company with an "honest-to-goodness" Structured ASIC offering is Altera with its HardCopy technology. The idea is that Altera can take your existing FPGA design (created using one of their FPGAs) and quickly and painlessly convert it into a pin- and package-compatible Structured ASIC equivalent. My understanding is that HardCopy accounts for around 5% of Altera's revenues, which is nothing to be sneezed at, let me tell you (personally, I would be more than happy to live on 5% of Altera's revenues!). In fact, many regard Altera as being one of the most successful Structured ASIC vendors on the planet, which is funny (ha ha) in a way because their raison d'etre is, of course, FPGAs.
Coming at things from a completely different direction, another interesting player in this area is AMI Semiconductor (AMIS). AMIS offers a range of Gate Array, Standard Cell, and Structured ASIC products. Of particular interest (to us) is that it's carved out a niche for itself in the FPGA-to-ASIC conversion market. Unlike Altera (which will only convert its own FPGAs), AMIS are happy to work with almost any FPGA technology. In addition to migrating the logical (functional) portion of the design, AMIS will also create a device that is pin- and package-compatible with the original FPGA.
One interesting point here is that the FPGA-to-ASIC conversion market typically lags the latest-and-greatest technology nodes by one to two years (you have to first get used to working with FPGAs at a new technology node and then create and prove your design before you even think about migrating it to an ASIC or Structured ASIC). This fact has allowed AMIS to come up with a really cunning strategy to reduce costs; first of all, AMIS has its base Structured ASIC wafers fabricated by TSMC at the 150-nm technology node, where these wafers comprise all of the silicon and polysilicon layers, along with all of the fixed metallization layers. The point is that the higher-level metallization layers – the ones used to actually customize the Structured ASIC – have much bigger geometries (the tracks are wider and generally "chunkier") than the lower layers. Thus, AMIS finishs off its Structured ASICs with 3 to 5 customized metallization layers that are applied using a cheap-and-cheerful 250-nm process. What a clever idea!
As opposed to the previous FPGA-to-ASIC scenario, some folks opt for a Structured ASIC implementation right from the "get-go." As we previously noted, Structured ASICs can be developed significantly cheaper and faster than their full-blown ASIC counterparts, which makes them ideal for mid-range production runs of say 50,000 (give or take 10,000 here or there).
There are a number of players in this arena. Some of the names that immediately spring to mind are AMI Semiconductor, ChipX, eASIC, and Faraday Technology. (As an aside, ChipX used to be known as Chip Express.) This reminds me of the time when the singer/artist Prince legally changed his name to an unpronounceable symbol. This obliged journalists and reporters to refer to him as "The artist formally known as Prince." When he eventually tired of the insanity and changed his name back to Prince, everyone got their own back by referring to him as "The artist formally known as a symbol." You have to laugh. But we digress…
The great thing about Structured ASICs is that there are lots of different ways of doing things, and each of the above companies has a different approach. As one example off the top of my head, the folks at eASIC have created a Structured ASIC fabric that combines FPGA-like SRAM-based lookup tables (LUTs) with customizable metallization layers. The point here is that different fabrics may be better suited to different applications, so if you intend to go for a Structured ASIC implementation you'll have to do your homework first (or I would be happy to do it for you for an exorbitant amount of money).
As opposed to creating and purveying actual Structured ASIC devices, some folks have opted to become third-party intellectual property (IP) providers. That is, they provide Structured ASIC fabric (and associated design tools) that you incorporate into your "Platform ASIC" (or SOC) design.
The idea here is that you create a "platform" that you will use as the basis for a suite of designs and design derivatives. This Platform ASIC may include one or more processor cores, buses, memory subsystems, peripheral functions, and so forth. All of these blocks will be highly-characterized, finely tuned, proven, robust, and set in stone (frozen in silicon). Thus, the Platform ASIC may also contain one or more blocks of Structured ASIC fabric, thereby providing a low-risk solution that allows you to customize your platform for different applications and evolve it to take account of any changes in protocols and standards.
Two players in this area are Lightspeed Logic and ViASIC. (Lightspeed Logic used to be known as Lightspeed Semiconductor. My head hurts!) As usual, both these folks have different "claims-to-fame." For example, ViASIC has developed a Structured ASIC fabric called ViaMask that requires the customization of only a single via layer. In addition to reducing mask costs and the time taken to get working parts back in your hands, this means that all of the delays associated with the device are highly characterized (well known) – and any signal integrity (SI) issues like crosstalk have already been resolved – which greatly facilitates timing closure and design closure (see also the “Standard Metal” topic below).
Now, one point to consider is that a lot of Structured ASIC fabrics are based on proprietary cells (logic functions). This means that when a fab introduces a new technology node, these cells have to be re-implemented from the ground up, which is expensive and – more importantly – time-consuming. To address this issue, Lightspeed has taken its original Structured ASIC fabric and recreated it using Standard Cell technology; that is, using cells from the foundry's standard libraries. Similarly, ViASIC has introduced a fabric called DuoMask that (a) requires the customization of only two via layers (see also the “Standard Metal” topic below) and (b) is based on Standard Cell technology. Using these standard library cells allows Lightspeed and ViASIC to dramatically increase the availability of their offering across multiple foundries, processes, and technology nodes (and reduce risk) by leveraging all of the work performed by the fab in qualifying a new process.
You know how it goes, there's always someone in the crowd who doesn’t fall into any of the usual categories (like the guy who insists on wearing golfing pants to formal dinners). And so we come to Triad Semiconductor which uses ViASIC's one-custom-via-layer technology to provide a rather cunning mixed-signal (analog and digital) Structured ASIC offering.
There’s one more Structured ASIC concept that deserves some mention before we turn our gaze toward the future. As we’ve previously noted, many Structured ASIC fabrics are based on proprietary cells (logic functions), while others are based on the standard cell libraries provided by the foundries.
On top of this underlying fabric we have the metallization and via layers that will eventually be used to configure the various logic functions at to form the tracks (wires) linking these functions. The point is that there are two primary techniques use to perform these tasks. One way is to use a relatively large number of routing layers (say 3, 4, or more) and associated via layers and to create the tracks on a custom basis. On the one hand this approach may result in relatively fast signals; on the other hand it increases the complexity of performing timing calculations and achieving timing closure, and it also opens the door to signal integrity issues.
The other technique is to pre-implement all of the track segments, and then use only one or two via layers to configure the underlying logic functions and to connect ("turn on/off") the various track segments. Referred to as "Standard Metal," this is the approach used by eASIC, Triad Semiconductor (which uses ViASIC's one-custom-via-layer technology to provide a rather cunning mixed-signal - i.e., analog and digital - Structured ASIC offering), and ViASIC. The advantage here is that the vast majority of parasitic effects and timing delays have been strongly pre-characterized, which greatly eases the task of performing timing calculations and achieving timing closure. Also, it means that the vast majority of any signal integrity issues have already been addressed by the Structured ASIC vendor.
As for the future…
So, what does the future hold for Structured ASICs? Well, that's the million dollar question, isn’t it? One fact that may have curtailed the widespread adoption of Structured ASICs thus far is the tremendous advances we've seen in FPGA architectures. These advances have allowed FPGAs to be used to implement complex functions and appear in products that would have been inconceivable only a few short years ago.
Having said this, I personally think the future holds a lot of promise for Structured ASIC technologies. We're already finding it difficult, expensive, and time-consuming to create designs at the 65-nm technology node. Things are set to get a lot harder at the forthcoming 45-nm node and below.
Of course, there is always going to be a market for full-blown ASICs for applications that require the highest possible levels of performance and the lowest possible power consumption, especially when these applications involve millions of units. However, the shear complexity of creating these designs and achieving timing-closure and design-closure – coupled with the extremely high cost of specialist tools and the incredibly high levels of expertise required – might well exclude a lot of design houses from this market. Another consideration is that new designs are required as soon as possible and market windows are shrinking; there's no point in creating the best ASIC in the world if it's going to be obsolete before you've finished developing it.
For all of these reasons, I think that we're going to see a dramatic upsurge in the use of Structured ASICs at some time in the future. Will it be at the 45-nm technology node or some later node? Who knows? Will one of the existing players end up dominating the field, or will someone suddenly leap onto center stage with a fanfare of trumpets and surprise us all with a completely new offering? Again, who knows? But one thing is for sure; it's going to be exciting finding out!
So what is a Platform FPGA?
And finally, we return to our original question, which was: "Just what is a Platform FPGA anyway?" Hmmm. I don’t know if there is a formal definition, but let's take a stab at working this out in our own minds.
First, let's remind ourselves that FPGA stands for "field-programmable gate array." When the first FPGA was presented to the market by Xilinx in 1985, it's fabric was basically a small array of configurable lookup tables and flip-flops. That is, this fabric looked very similar to a traditional gate array form of ASIC, hence the "field-programmable gate array" moniker.
Over time, this core FPGA fabric has dramatically increased in capacity and quantity, and it's been augmented with blocks of hard IP, such as RAMs, multipliers, general-purpose processor cores, DSP cores, and so forth. For their own reasons, FPGA vendors have started to refer to these "great big hairy devices" as "Platform FPGAs."
If you cast your mind back to our earlier discussions, we described a Platform ASIC as being a "platform" that can be used as the basis for a suite of designs and design derivatives. We also said that this platform may include one or more processor cores, buses, memory subsystems, peripheral functions, and so forth. Also, that these blocks may be combined with one or more blocks of (customizable) Structured ASIC fabric. Well, if you look at today's high-end FPGAs from one perspective, they sort of boil down to the same thing, which would justify the Platform FPGA appellation.
On the other hand … I'm mentally wrestling with the fact that the vast bulk of the FPGA can be totally reconfigured, thereby making the device do something completely different, in which case we might ask: "Where is the platform?" But then another voice pops into my head (I live an interesting life) pointing out that there's an increasing ability to selectively configure only portions of an FPGA. On this basis, I can envisage someone creating a base design that results in a known (fixed) configuration for the majority of the FPGA, but that this design could contain blocks of uncommitted FPGA fabric that can be selectively configured to provide different derivatives of the base design. In this case, this would truly be a platform-based approach.
Parting is such sweet sorrow
And so, in closing, my final message (for what it's worth) is that if you are at all confused by any of this, don't panic, because you;re not alone. Different folks have completely different points of view and may well present many of the concepts discussed here in a completely different light.
On the other hand, I think that together we've painted a "big picture" that hopefully brings a myriad of different topics into slightly sharper focus. What will be interesting is to see what the various companies think when they come to see this article. Will they email me proclaiming that I've given a masterly summation of a complex field, or will they hint (or say outright) that I'm a blithering idiot who shouldn’t be allowed out on his own without someone to watch over me and keep me out of trouble. Only time will tell.
Structured ASICs and Platform FPGAs: Part 1
By Clive (Max) Maxfield. Max is president of TechBites Interactive (www.TechBites.com), a marketing consultancy firm specializing in high-tech. In addition to authoring "Bebop to the Boolean Boogie (An Unconventional Guide to Electronics)" and "The Design Warrior's Guide to FPGAs (Devices, Tools, and Flows)", Max is the co-author of How Computers Do Math (ISBN: 0471732788) featuring the pedagogical and phantasmagorical virtual DIY Calculator. In addition to being a hero, trendsetter, and leader of fashion, Max is widely regarded as being an expert in all aspects of computing and electronics (at least by his mother). Max was once referred to as "an industry notable" and a "semiconductor design expert" by someone famous who wasn't prompted, coerced, or remunerated in any way.