July 14, 2006 -- The IEEE has recently ratified SystemVerilog and SystemC to be official IEEE standards known as IEEE Std. 1800-2005 and IEEE Std. 1666-2005 respectively. This step is the last in a standardization path that has included incubation, market development and ecosystem cultivation of the languages within their respective consortia, namely Accellera and Open SystemC Initiative (OSCI). The SystemC and SystemVerilog design and verification languages were developed to deliver exponential increases in design productivity in response to the industry’s perennial challenge – continuing exponential increases in design and verification complexity. These languages are increasingly used in a complementary manner in system-on-chip (SOC) design.
Despite their complementary nature, however, there remains some confusion fueled by comparative language analyses to suggest that designers are confronted with a choice between them. But design and verification challenges have pushed mixed use of SystemC and SystemVerilog.
SOC design productivity challenge
An SOC is literally a system on a chip, consisting of both silicon and embedded software. Its design involves complex algorithm and architecture development and analysis similar to that performed in system design – a trade-off process that determines critical metrics, such as SOC performance and power consumption. With the 65-nm technology node nearing readiness for mainstream use, design and verification complexity is clearly on the increase.
Consequently, design tools must deliver orders-of-magnitude improvement in productivity at both architectural and implementation (RTL and physical) levels. Moreover, tools must support a methodology that enables the early development of embedded application and system software, long before the availability of the RTL design or silicon prototype. Failure to achieve the requisite improvements in design productivity would result in missed market windows, and exploding design costs.
SystemC: The SOC system-level modeling language
SystemC was developed in response to demands for a standard electronic system-level (ESL) language for SOC designers using C/C++. It is a single, unified design and verification language that expresses architectural and other system-level attributes in the form of open-source C++ classes. It enables design and verification at the system level, independent of any detailed hardware and software implementation, as well as enabling co-verification with RTL design. This higher level of abstraction enables considerably faster, more productive architectural trade-off analysis, design and redesign than is possible at the more detailed RT-Level. Furthermore, verification of system architecture and other system-level attributes is orders of magnitude faster than that at the pin-accurate, timing accurate RT-Level.
SystemC itself is purely a version of C++, adapted and standardized by OSCI for the purposes of system-level design. The IEEE 1666 Language Reference Manual (LRM) now defines SystemC semantics to provide an unambiguous definition of the SystemC language. It enables EDA tool and IP developers to provide simulators, models, and system-level design tools that conform to the SystemC standard.
SystemVerilog: The S0C system-level design and verification language
SystemVerilog, the first hardware description and verification language (HDVL), is a major extension of the established IEEE 1364 Verilog-2001 language, and was developed to dramatically improve productivity in the development of large gate count, bus-intensive designs. Now an IEEE standard and know as IEEE Std. 1800-2005, SystemVerilog is targeted primarily at the behavioral-to-GDSII part of the SOC design flow. However, SystemVerilog also supports transaction-level modeling at the "transaction" level of abstraction. This verification overlap between SystemC and SystemVerilog constitutes an invaluable design and verification link from the system-level to chip implementation. SystemVerilog’s Direct Programming Interface (DPI) enables it to "call" C/C++/SystemC functions, and vice versa, making SystemVerilog the first Verilog-based language to enable efficient co-simulation of SystemVerilog and SystemC blocks.
SystemVerilog’s important SOC-targeted improvements over Verilog-2001 include:
- A set of extensions to address advanced design requirements. Examples include modeling interfaces that greatly accelerate the development of bus-intensive designs; removal of restrictions on module port connections, allowing any data type on each side of the port; extended data types to allow C modeling; enhanced IP protection by nesting modules locally to their parent module, and not visible to other parts of the design, etc.
- A new assertion mechanism to support assertion-based verification (ABV), whereby assertion information is built into the language, eliminating the need for the special modules, pragmas or PLI calls used in Verilog. The mechanism helps to avoid recoding errors, increase test accuracy, simplify the testbench, and enable test reuse. For the first time, assertions added within a design can provide the real intent of a designer in terms of functionality and constraints. These embedded assertions can be verified through simulation before applying any formal or dynamic technique to verify the design. In essence, the embedded assertion provides full visibility and controllability of internal nodes to all tools, and enable new breed of tools such as assertion-based synthesis. SystemVerilog Assertions (SVA) enable advanced "design for verification" methodology.
- New features to support testbenches and hardware models that utilize object-oriented techniques. Combining the SystemVerilog Interface method with object-oriented testbench creation techniques enables a powerful advanced constraint-driven verification methodology for verification engineers that surpass all existing capabilities today. Specifically, the assertions used by the design engineer expressed as a design property become a constraint that the verification engineer must prove hold true or are covered during verification. Further, the assertions created by the design engineer and used or extended during the verification phase by the verification engineer can be reused in an SOC when design-reuse or IP-based design methodologies are utilized.
The IEEE Std. 1800-2005 SystemVerilog includes high level synthesis constructs, such as data path; full API support, testbench and assertion enhancements, and transaction level modeling enhancements. Moreover, Accellera is actively considering enhancements such as the synchronization of SystemVerilog with Verilog-AMS (analog/mixed signal) in Verilog-AMS 3.0.
Accellera, OSCI and IEEE
Accellera initiated use of the IEEE Corporate Program for all its standards. Since then, numerous other organizations have joined in the use of this program, including OSCI. The IEEE is the standards organization of the electronics industry. It is both the steward and the arbiter of standards that enable the electronics industry to maximize inter-operability and, thereby, innovation. Through the corporate program, the same efficiency in creating the standards in Accellera and OSCI is brought to the IEEE process as well.
Accellera and OSCI have acted as focal points and coordinators of communities of users and suppliers to drive the rapid development of two complementary standards in response to a burgeoning SOC design challenge. Both organizations recently gained approval by IEEE for these two standards as the last step in their standardization process.
It is clear from the descriptions of SystemC and SystemVerilog that the two standards are largely complementary in the SOC design process. SystemC supports a system-level methodology above the RT-level with high-speed models capable of hardware and software interaction analysis, while SystemVerilog supports system chip implementation and verification methodology, with a transaction-level bridge to the SystemC system-level domain. A robust and effective SOC design flow will leverage both SystemC and SystemVerilog together to design and verify SoCs.
By Dennis Brophy, Vice-Chair, Accellera
Go to the Accellera website to learn more.