October 17, 2006 -- The trend to combine multiple functions on one piece of silicon to reduce cost, power consumption, and manufacturing and test time is gathering momentum, driven by requirements for smaller, less expensive high performance products. The relentless push to pack more and more features into smaller and smaller packages make SOC a natural, but it carries a host of other advantages as well. A reduction in high-volume manufacturing costs and component inventories can be expected, as can higher reliability. Since CMOS technology is usually employed, better power management and inherently lower power consumption raise the overall efficiency of an SOC design relative to a discrete component approach.

With all these advantages, it is essential that PWB circuit design engineers consider where SOC may apply to their product developments. However, even the best board-level designers will find a whole new set of issues arise as they seek to transfer a design to SOC, issues for which their training and experience may not have prepared them. This is the case whether an SOC design is attempted in-house or a development partner is engaged. Gaining an understanding of what some of those challenges are and how they can be addressed will increase the odds of successfully transitioning a design to SOC.

The challenges of SOC design

Besides the obvious difference in scale, an SOC design diverges in a number of more fundamental ways from a PWB design. There are significant differences in the basic technologies, CAD tools, and design and test methodologies. A fundamental shift in approach has to take place when moving from PWB circuit design to SOC. The voltage-mode thinking that accompanies conventional circuit design has to be replaced with current-mode approaches. Resistors commonly used in PWB designs are avoided wherever possible in SOC layouts because of the space they occupy. Instead, resistor dividers are replaced by current mirrors, allowing current going into one node to be matched by an equal amount (or some other fixed proportion) leaving another.

Large passive devices in discrete circuitry give way to capacitors and resistors limited in value to about 20pfand 200K, respectively, in SOC designs. Ten or twenty transistors in the average PWB design may swell to tens of thousands in a typical SOC design. The complexity that leads to increased size and cost in discrete circuits actually becomes a functional requirement of SOC technology, as well as an invitation to add more features and capability simply because it is possible. Discrete circuit techniques relying on accurate voltages and predictable component tolerances give way to 20-40% typical variation in SOC component values. This is offset by design techniques that rely on the fact that, even though SOC component values vary, they do so together and can therefore be matched to a very tight tolerance.

Thought of another way, constraints arising from available components in conventional designs are replaced by constraints of available SOC technology. Circuit modifications, often relatively easy to apply to a PWB design become much more difficult to implement in an SOC design. Consequently, good circuit models are not only available for SOC designs but are critical to success, unlike discrete designs where - even with the tools available - it is often simpler to breadboard and debug a circuit design rather than spend the time to model and simulate it.

Despite all these differences, it may be tempting to believe that an effective SOC design team can be developed by using in-house talent or bringing in one or two experienced IC designers. However, neither approach has proven successful in practice. Experience has shown four to six experienced IC designers are required to reach a critical design mass. This is true for several reasons. Few SOC projects are small enough to be handled by one or even two designers, and it would be rare to find one or two designers with sufficient skills in all the various areas required – system level and transistor level design, physical layout, device physics and test – to name a few. Success in SOC design is a team effort, but it is also a process, building on the skill and experience gained from previous designs. Important as well is access to a broad library of circuits built up over time – proven sub-functional blocks used in previous designs which are readily adaptable and applicable to new projects. Circuit libraries offered by most foundries include useful basic digital blocks, but most analog blocks are usually too specialized to be applicable to more generalized designs. Another major hurdle for an in-house team is the need to develop an IC design specification for each project. This basic requirement will almost certainly be beyond the skill and experience level of most PWB design firms and require the assistance of an IC design house.

Bringing in a group of IC designers to form a team isn't necessarily the answer, either. Start-up costs are high and may prove to be prohibitive for many companies. Besides the added salary costs, expensive CAD tools will be a necessity – tools that enable integrated design flow among the team members and allow efficient reuse of existing standard cells. Another common hurdle to be faced is the fact that many smaller companies don't have a sufficient number of new projects to keep their team busy and may lose some of their designers to IC design firms or other companies with a more consistent flow of interesting projects. In addition, the importance of having a team which has worked together should not be discounted. This means that, unless an entire team is hired en masse, the ramp-up to a successful design effort may be frustratingly slow while the team members leam how to meld their skills. Experience has also shown that it normally takes a few projects for a team to ramp up to an adequate level of efficiency. A PWB design company aware of these challenges and willing to forge on must also be prepared to make a significant outlay for laboratory test equipment that is specific to SOC test, such as analytical probe stations and laser cutters. And last, but not least, proven program management teams must be in place which can properly administer complex design efforts characteristic of SOC projects.

Moving forward

If your company is determined to delve into SOC products but decides it doesn't want to make the commitment to develop a team in-house, the next step is to seek out a qualified development partner, one with demonstrable success in SOC design. This step is not without its pitfalls, but becoming aware of the proper steps to take and problems to avoid will accelerate the process. As could be expected, choosing the right SOC development partner is a critical step. Since this must be a close partnership to be successful, an open communication path between your company and the SOC development firm is essential. You need to feel confident that the SOC developer is capable of providing adequate systems engineering capability and demonstrates an understanding of PWB electronic systems. It will generally take more than superficial knowledge to grasp the requirements and nuances of the application and the PWB solution. Choosing the right SOC partner may mean the difference between a solution minimally suitable for high volume production and leveraging technology for an optimal SOC solution.

The first milestone in the partnership is developing the quote. A fixed bid quote with schedule and cost commitments should be generated to meet your application requirements. It is not uncommon to require a week or more of intensive discussions between the SOC design team and your designers, just to arrive at the point where the SOC developer can begin to develop the quote, and several weeks more to complete it. That is the case because development of a comprehensive quote involves initial system design, and a responsible design firm won't begin to assemble a quote until your design and its application are both thoroughly understood. For this reason, receiving an immediate quote should be cause for concern regarding the capability of the SOC developer. Depending on the value of the design assignment and intellectual property (IP) that it will generate, you may be asked to pay for part or all of systems work required for producing a comprehensive and meaningful quote. Such a quote is usually provided separately and paid with no commitment to continue to the development phase. It is important to recognize that during this phase your SOC design partner is providing value and not just hours.

These pre-bid discussions also provide an opportunity to assess the capability of the SOC firm, build rapport with its team, and judge whether the necessary level of communication exists to complete a successful design collaboration. The company history and financial stability should be reviewed as part of this process. You can expect to go through a few spins before going into production and you want a development partner that will be around for the inevitable chip debug process, as well as for any production issues that may arise. This is also a good time to make sure the SOC developer has completed successful designs and products technologically similar to your own. For example, it is unwise to expect an SOC firm to produce your RF design when its experience has been entirely in baseband product development. Although SOC developers have sold their general design capabilities successfully in the past, more specific applications experience is currently expected and demanded. To assist in such an assessment, a reputable SOC developer should be ready and willing to provide examples of production released products it has developed. In addition, a visit to the developer's facilities is recommended to assess systems capability, design flow, transistor level design and physical layout competence and qualification testing capability.

Issues for discussion

There are a host of issues that should be part of the discussion leading to development of a quote. As already noted, the application requirements and the SOC specification are fundamental, but make sure there is a thorough discussion of the important features and benefits of the existing PWB solution and how they will be addressed in the SOC product. The SOC package size, cost and thermal considerations should be reviewed, as well as what external components will be necessary. Sensitive circuitry issues and susceptibility to ground and supply bounce should be discussed, as well as potential switching and high current problems arising within the SOC device. Testability at the wafer, package and board level, and test vectors for simulations should be explained, and the SOC developer should provide Spice models for external components, package pins and external components. Expected yield, worst-case models, matching, temperature specifications and expected life should be clarified. An explanation of production trimming requirements and whether there will be EEPROM, fuse or laser trim should be included. ESD considerations, particularly important for CMOS devices, should be addressed. The expected schedule for system level and transistor level design phases should be discussed, as well as the SOC developer's normal method of integrating physical layout and transistor level design elements. Procedures and average timetables for preliminary, critical and final design reviews should be adequately reviewed. The tapeout to foundry procedure and expected schedule should be discussed, as well as prototype test and production support provided.

Production support is critical to developing an ongoing relationship with your SOC development partner. You want to be sure any production issues will be quickly and thoroughly addressed, and that the SOC partner is staffed and prepared to furnish such support. You will want to understand procedures and processes used in chip qualification, yield expectations and procedures to address low yields. Production test procedures should be clarified, including interface issues with the foundry.

With the ever-increasing importance of IP issues, this area should be thoroughly explored and completely understood as part of the initial quote. The rights and responsibilities of both your company and the SOC partner should be agreed upon and included in any written agreements. Provisions for single or multiple use, license fees, royalties and related items should be discussed and agreed upon. There is a trend toward IP/value based agreements where your firm owns the top level design but the SOC developer owns and licenses the underlying IP. Be sure these issues are thoroughly discussed and included in your agreement.

Any move from conventional PWB design to SOC has its share of both hazards and potential rewards, but for many companies the benefits warrant a thorough examination of such a step. Using the guidelines discussed here, you should develop an understanding of the SOC design process and the benefits and limitations of an SOC design. There is no fixed rule determining whether the best approach for your company is to develop your own team, engage a development partner, or refrain for using SOC based products. There are numerous time and financial considerations that need to be explored as they relate to your specific circumstances. If you make the commitment to develop an SOC design in-house, you will also want to lay the proper groundwork for a team effort that leads to long term product success, not just a short term effort ending with a single product. Team growth is a process that requires time, proper management and commitment of resources to reach an optimal level of efficiency. If your company has several divisions which could be supported by an in-house SOC development team, your chances of assembling a group that can become a long term asset to the company increase. And, even if the SOC path doesn't make sense at this point, an understanding of the important underlying considerations will be valuable if you re-evaluate your need for SOC products at a later date. It is expected that the overall growth of SOC technology, combined with demands for more features in smaller, less expensive, low power products will make the transition from board level design to systems on a chip an important step for the success of many companies.

By Edward P. Coleman. Edward is the Principal PM Design Engineer, Integrated Circuit Designs, Inc.