July 6, 2007 -- In the traditional ASIC design flow, the sign-off stage was a key, well-defined point in the chip-making process. The designers would complete their front-end design and gate-level implementation, run timing sign-off using a static timing analysis tool, and hand the design to the ASIC foundry along with the timing constraints. The ASIC foundry would complete the back-end design with those constraints and provide timing information back to the design team, which in its turn would re-run static timing analysis to verify that, as far as it was possible to be sure, the chip would work at the required performance.
If all went well, the design and manufacturing teams would meet and agree to "sign-off" the design. In essence, the customer would outline a set of design performance criteria and a netlist known to meet those criteria, then the ASIC foundry would verify that those criteria would be met by the chip it intended to manufacture. The design was therefore declared “good,” and if there were to be any future issues with respect to silicon failure, responsibilities were clearly defined.
COT changes sign-off process
But in these days of the fabless model and customer-owned tooling (COT), the meaning of timing sign-off has changed dramatically. The foundry will certify its Spice models, DRC and LVS runsets, extraction models and IP libraries, but provide few solid guarantees beyond that point. As the industry has become less integrated, the design team has had to take responsibility for physical design closure with the adoption of a COT-based flow. Timing sign-off has moved to an internal customer criterion of readiness versus a formal handoff criterion to the foundry.
That does not mean that the importance of sign-off has diminished – far from it. If anything, sign-off tools are more critical than ever. Ahead of any other part of the flow, design teams need to trust their own sign-off processes to pinpoint problems prior to manufacturing. Only in this way can they reduce risk to an acceptable level, ensure design integrity, and keep design costs in check.
As a result, sign-off tools have evolved in two very important ways over the last several years. First, a static timing analysis tool now provides much more than just an accurate timing engine via static analysis and delay calculations. For example, today’s best solutions include signal-integrity analysis that provides advanced delay calculation with crosstalk and noise effects, as well as integrated gate-level power-analysis capabilities. Tight links to other tools in the flow that examine parasitic extraction and transistor-level modeling are also important.
The second evolutionary consequence is the need for tighter links between design implementation and sign-off. With the customer assuming responsibility for design closure in a COT flow, it is critical that the path between implementation and sign-off be predictable. Poor correlation between design and sign-off increases the risk of costly and time-consuming iterations back to place and route. Adding new sign-off criteria, such as power and signal integrity, substantially increases this risk if the design tools cannot accurately predict sign-off.
As the industry has adjusted to these long-recognized developments, another potentially more disruptive factor has reared its head: increased process variation. At 65 and 45nm, the effects of inter-die and intra-die variations become significant — timing, parasitic extraction, signal integrity, and a host of other factors need to be dealt with by variation-aware techniques.
The revolutionary nature of this change in thinking has led many in the industry to speculate that the time is right for a corresponding revolutionary change in sign-off tools. The move to statistical techniques, they maintain, requires wholesale re-tooling, while increased integration means that it makes sense to use a unified timing engine throughout the implementation flow to improve correlation between tools.
At Synopsys, the conclusion is that quite the reverse is true. With re-spins more costly than ever, and responsibility now firmly with the customer, it makes little sense to increase risk by throwing away trusted techniques and gold-standard tools. Sign-off is an area that requires a tremendous investment, not only from the EDA provider, but also from the design and verification teams who use and must qualify the tools. A static timing analysis tool such as PrimeTime® becomes trusted, not only because of the time and person-resources invested in building the tool itself, but because of its comprehensive support and feature set. Such a tool also needs to be honed by the in-use experiences and contributions of a wide range of customers and to undergo rigorous vendor and foundry qualification with a variety of circuit types and design styles over a long period of time. Every design team will also need to devote substantial time and effort to tune its sign-off methodology to their particular flow and design style.
Synopsys has maintained an evolutionary approach to developing its sign-off offering, seeking to preserve the trusted nature of the tools and yet still introducing new technology when and where required. This method is exemplified by the progressive introduction of statistical timing analysis and other variation-aware techniques, with seamless integration into static timing analysis, rather than starting from scratch and re-tooling.
This evolution works on several levels. In many cases, design teams are still struggling to come to terms with the details of variation-aware design, as well as with the higher-level questions of whether – and when – they need to know about it. EDA vendors should, therefore, allow customers to adopt new technology at their own pace, retaining a foundation that they trust, rather than expecting them to make a sudden jump. Thus, the introduction of variation-aware analysis by integrating statistical technology within existing parasitic extraction and static timing analysis tools delivers enhanced analysis capabilities with the benefits of tried, trusted, and accurate tools.
The reason for this is a statistical approach alone does not provide a complete solution to model variation. Functional modes, environmental temperature and voltage range, temporal thermal effects, IR-drop, and signal integrity are all conditions that must be modelled in sign-off but are either difficult or cannot be captured statistically. So corners, bounded techniques, margining, cross-talk analysis, multi-scenario and statistical analysis, must all work together to provide a complete solution.
In addition, statistically-enabled timing analysis tools must meet all the requirements necessary for timing sign-off — accurate delay calculation, accurate delay propagation, correct handling of topological correlation (convergence/re-convergence), correct handling and interpretation of design constraints, reporting, what-if-analysis, debugging features, ECO flow integration, and so on — capabilities that today already come as an integral part of a quality static timing analysis suite.
Given these fundamental requirements, the best approach is to build on existing tools that designers already trust. This lets designers introduce new margin reductions techniques while still handling all of the sign-off requirements needed to insure working silicon.
Implementation and correlation
Though top-down integration into the implementation flow looks attractive on paper, sign-off tools need to be designed with attention focused downstream, toward manufacturing — the inviolable need for correlation is with Spice and the silicon itself. To achieve this requires uncompromised accuracy from the sign-off tool.
Implementation tools, in contrast, have to run as fast as possible to improve designer productivity, and will inevitably need to trade some degree of accuracy for the sake of performance. The key is to optimize this trade-off and to test extensively to ensure a good correlation between place-and-route and sign-off tools. The importance of this cannot be overstated.
This bottom-up approach extends to front-end correlation with technology such as topographical synthesis to better predict post-layout design performance from the point of view of timing, power, and area.
As the industry moves to 45-nm production, design teams are extremely wary of moving away from tried and trusted gold-standard sign-off tools. While, for many, timing sign-off may no longer exist as formal hand-off deliverable between themselves and their foundry, it’s more important than ever to silicon success. Designers, therefore, require an evolutionary approach, in which statistical techniques and other variation-aware technologies take their place beside some of the most robustly tested and well-trusted tools and techniques in the industry today.
By Robert Hoogenstryd.
Hoogenstryd is Director of Marketing for design analysis and sign-off within the implementation group of Synopsys, Inc. He has been involved in the EDA industry for over 18 years having held a number of roles in applications engineering, marketing and sales within pioneering companies such as Daisy Systems, Silicon Compiler Systems, Mentor Graphics and Silicon Metrics.
Go to the Synopsys, Inc. website to learn more.