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 Category: SOCcentral Feature Articles & Columns: Feature Articles: Thursday, April 24, 2014
Silicon Validation via LFD Simulation   Featured
Contributor: Mentor Graphics Corp.
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August 6, 2007 -- Razrs, Krazrs, Blackberries, iPhones. Cars that park themselves, tell you when they need servicing and show you the fastest route to your destination. Consumers today, particularly electronics consumers, are demanding products that are cheaper, faster, smaller, more powerful and more versatile, and they want them now. This incessant demand for innovation and redesign is resulting not only in faster IC design and manufacturing cycle times, but also shorter product lifecycles than ever before. As chip size drops below 65nm, add in escalating design and manufacturing costs incurred to achieve satisfactory yields, and it’s clear that a new strategy is needed.

Beyond traditional DRC

At 90nm and below, DRC compliance alone is insufficient to avoid layouts that can result in physical defects or performance variation that reduce yield. Adding “recommended rules,” or design-for-manufacturability (DFM) guidelines, to the design verification process helps reduce the impact of these yield issues by identifying potentially critical configurations, or “hot spots,” but doesn’t completely solve the issue of layout distortion due to lithographic process windows.

Above 65nm, resolution enhancement technology (RET) could compensate adequately for these variations between design and production, without significantly impinging on production time or budgets.But at 65nm and below, modifications to a photomask are no longer enough to ensure image fidelity, and they are no longer practical. The addition of optimal proximity correction (OPC) features to a design not only creates even more points for potential production defects, but also exponentially increases the data size of the mask layout. Respins due to unacceptable silicon results drastically impact both design and production time and cost.

Designers need a new strategy to help them anticipate how a physical layout, especially at the cell level, can be designed so that feature fidelity is preserved across the manufacturing process window, not just at nominal dose and focus. By moving this validation into the design process, designers can find and eliminate or revise those design elements that are not likely to produce the desired physical results, reducing the costly and time-consuming respins needed to achieve acceptable yield.

The term now used to describe this strategy, Litho-Friendly Design (LFD), was introduced and specifically mentioned within the ITRS roadmap as a necessity for base layer optimization starting at 65nm. LFD can be defined as an integrated design process comprising:
  • RET manipulations to be applied to the physical design.
  • Process window simulations to identify susceptible patterns.
  • Layout enhancements to improve results of the highest-risk layout structures.

A process window may be defined by changing an input factor by a fixed amount and measuring the result over a grid of points on a test chip. This process can be repeated for a number of key variables that exist in the fabrication process. Process windows can be described two ways:
  • For one input parameter, the inherent effect of a change in that parameter that results in an effect on any other parameters that may be plotted in two (or more) dimensions.
  • For two input parameters, any description of the tradeoff between the tolerance of one input parameter and the tolerance of other input parameters.

Simulation lets designers model the effect of process windows on designs using statistical methods, and improve chip yields by identifying those design features most likely to result in physical failures at some point within the process window.

Litho-friendly design (LFD) tools let designers analyze a DRC-compliant design for its manufacturability by simulating the effects of production-line lithographic process adjustments on feature reproduction. In the LFD process, an optical rule check (ORC) simulates the lithographic pattern transfer of the chip layout after the application of RET adjustments.

The four most common yield failure configurations include: pinching, bridging, area overlap, and critical dimension (CD) variability. Predictions of these configurations are compiled into LFD rules. During the design process, the designer uses these LFD rules to analyze the flagged areas. LFD failure rules identify areas in which a variation in printing (in response to process variation) is likely to cause critical errors from a manufacturing, timing, and power standpoint. While typical design-rule violations can be fixed by edge-movement (compacting features) or morphological (clipping corners) changes, LFD rule failures almost always require topological changes.

Check

Parameter

Minimum width check

Printed: minimum free width, range of violation, mean free width
Drawn: mean free width

Pinching check

Checks for pinching (opens) over the process window
Parameter: range of violation

Minimum space check

Printed: minimum free space, range of violation, mean free space
Drawn: mean free width

Bridging check

Checks for bridging (shorts) over the process window
Parameter: range of violation

Minimum area overlap check

Printed: relative printed contact area, minimum contact area
Drawn: designed contact area

Process Variability Index

Regular process variation bands: mean width, area
Absolute process variation bands: mean width, area

Table 1. Sample LFD failure checks.


The models created from the layout simulations can be compared statistically to determine which design modifications are most likely to produce the highest yield. Simulation results can include recommendations about areas where modifications to the layout would most likely improve yield. For example, Mentor Graphic’s Calibre LFD product calculates a Design Variability Index, or DVI, as a way to measure how resilient the design is to process variations. A lower DVI value represents a more resilient design (see Figure 1). The DVI is used to compare different layout implementations and help designers select the one with the least sensitivity to variation.

Figure 1. The DVI guides the layout designers in making the design more robust against process variations.


Model verification

Inconsistencies between simulation and the wafer measure are due primarily to two factors:
  • Measurement errors
    • Position errors (asymmetric nature of the measurement pattern)
    • SEM charging
    • Other pattern loading effects
  • Modeling inaccuracies
    • Non-physical nature of resist model
    • Numerical approximations within optical model
    • Fitness assumptions

In the past, verification of optical rule models was based on test patterns. However, despite continuous improvement of test patterns, they do not fully cover the variety of printed patterns occurring in a realistic layout. Test patterns will never cover all imaging situations, since many test patterns cannot be measured with appropriate accuracy. Imaging conditions poorly covered by test patterns include catastrophic scenarios such as:
  • Printing sub-resolution assist features (SRAFs)
  • Pinching (opens)
  • Bridging (shorts)

This is particularly true for LFD models, which are intended to detect points where image quality becomes poor in a layout. LFD models must cover a finite process window of at least the 3s conditions for dose and focus of the lithographic process. Two types of LFD models are currently in use:
  • Nominal condition models calibrated using test patterns printed at nominal conditions. Validity of these models is verified in a second step using measurements from test patterns and SEM images taken over the whole process window.
  • Process window models calibrated on the basis of test patterns printed on actual silicon over the full process window. Availability of well-printing test patterns impedes the calibration of such models.

At present, full chip hardware analysis is the most reliable benchmark for determining the validity of ORC and LFD-process models.

Silicon validation

LFD models calibrate the simulations to the specific lithographic processes in use by a mask house, as well as the specifications applied during verification. Because LFD provides the ability to run simulations against a particular lithographic process window, designers get a clearer picture of how the layout will print under production conditions.

Foundries are now providing LFD “process kits” to enable designers to incorporate LFD during layout generation phase. With an LFD process kit that encompasses RET recipes, process models, and parameterizable rules, designers can run the LFD simulations to see how a layout will print across the lithographic process window in use at that foundry. While the kit contains all the data pertaining to pattern transfer, what the designer sees and works in is very much like a DRC environment.

The need for cooperation and collaboration among design houses, mask makers, and foundries is potentially the biggest factor in the race to achieve acceptable yields on chips manufactured with processes below 65nm in feature size.

Even independent device manufacturers (IDMs) can benefit from the use of LFD. Naturally, IDMs have an easier time establishing and controlling new process flows than the independent design houses, because the IDMs control both the design and the fabrication process internally. But by adding LFD processes to their existing flow, IDMs can make layout modification trade-offs at the earliest stages of design creation, and dramatically improve layout robustness across the process window.

Over time, as designers become used to working with LFD models, they will learn what design features work best with the manufacturing processes used for 65nm and below. This knowledge will naturally lead to future designs that are "LFD clean" with a minimum of verification time and resources.

A real world experience

The value and practicality of LFD is not just theoretical. The benefits of implementing a lithographic process verification flow in the design phase were demonstrated in a joint project between Infineon Technologies AG, Chartered Semiconductor Manufacturing and Mentor Graphics.

In this project, a set of experiments were designed to test the value of implementing LFD model-based physical verification in conjunction with traditional DRC compliance on a 65nm design. The experiments were run on a standard Infineon cell library manufactured in Chartered’s Fab 7, and included lithography checks for Minimum Width (pinching), Minimum Space (bridging), Minimum Area Overlap and Process Variability Index.

Physical measurements on real test wafers processed with controlled dose and focus parameters correlated closely with results generated from the LFD simulations, demonstrating that the use of LFD could significantly reduce the need for test die and subsequent respins.

The other conclusion of the project was that DRC compliance alone was insufficient to prevent production hot spots. With further investigation, the team determined that most of the hot spots could be attributed to a small number of cells, and that these hot spots could be “ranked” by severity and yield impact. Using these rankings, designers could contribute to significant yield improvements by modifying a relatively small number of layout hot spots prior to manufacturing.

The results of this project were presented at the 2007 SPIE Advanced Lithography conference and documented in the conference proceedings (März, R., Peter, K., Grondahl, S., Keiner, K., Choi, B.I., Quek, S.F., et al. (2007). Hardware Verification of Litho-Friendly Design (LfD) Methodologies. In A.K.K. Wong and V.K. Singh (Eds.), Design for Manufacturability through Design-Process Integration, Proc. Of SPIE Vol. 6521, 65210M-1 ).

Using LFD allows designers to achieve “silicon validation” before tapeout to ensure higher and faster yields for advanced process nodes. By spotting and preventing potential design weaknesses before any fabrication begins, not only can time and resources be conserved, but yield and performance goals can be achieved.

Our experience has demonstrated that LFD is a critical success factor at 65nm and below. The need to detect physical printability issues as early as possible to avoid delays caused by layout changes and design iterations is even more important and valuable as product lifetimes decrease. Achieving yield and performance goals quickly reduces time-to-market and increases the likelihood of a profitable run and competitive advantage.

By Jean-Marie Brunet.

Jean-Marie is the LFD market development manager, Design to Silicon division, at Mentor Graphics Corp. He has more than 10 years of IC design and design management experience in the development and delivery of complex nanometer designs. He may be contacted at jm_brunet@mentor.com.

Go to the Mentor Graphics Corp. website to learn more.

Keywords: SOCcentral, Mentor Graphics, design for manufacturing, design-for-manufacturing, DFM, DRC/ERC/LVS, EDA tools,
488/23414 8/6/2007 9458 9458
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