November 5, 2007 -- Though yield learning has been applied for
generations of semiconductor process technologies to improve product yields and
profits, the techniques both available and in use today are rapidly expanding. First, the impact of systematic and lithographic issues is
increasing exponentially. Many traditional yield-learning techniques are quite
effective at reducing random defects, but often prove ineffective or
insufficient against new classes of defects and process variations. Second,
there is now widespread recognition that the interface between design and
manufacturing cannot continue to be a one-time, one-way step whereby the design
passes a fixed and fairly generic set of manufacturability rules.
Design-for-manufacturability (DFM) has driven a whole new industry focused on
helping designers avoid complex manufacturing issues, and has given process
engineers a clearer understanding of complex design information. Third, wafer
sort and final package test data represent a valuable but mostly untapped source
of yield-learning information. This article will describe how a production
solution was developed to apply diagnostics to production test failures and then
turn that information into usable data for yield learning.
Scan-based diagnostics
Almost all digital designs today use structured design-for-test (DFT)
techniques to apply electrical tests for wafer sort and final package test. The
most common technique is full-scan, which provides several fundamental benefits.
First, since most circuit states can be directly controlled and observed during
test, automatic test pattern generation (ATPG) can reliably and quickly produce
very high fault coverage scan tests, even on very large designs. Second, and
directly relevant for yield learning, failure diagnostics can reliably and
quickly isolate the cause of scan test failures down to a small number of
potential defect locations called fault candidates.
Historically, the most common application of scan-based diagnostics has been
to isolate defect locations on a handful of parts that have been selected for
engineering-intensive root cause analysis. These might be field returns showing
a potential reliability issue, or these might represent a common failing
“signature” that is causing yield loss. For such cases, diagnostics are a
required step before performing physical failure analysis on each failing part.
Physical failure analysis is a labor-intensive, time-consuming and expensive
process and can be considered only if there are a very small set of cells and
nets to navigate. To summarize, the traditional application of scan-based
diagnostics has been to make physical failure analysis possible and more
efficient.
Volume diagnostics
Although the method just described can be effective for resolving the failure
mechanism on individual parts, one important question remains: How does the
process engineer know whether he has identified a random defect or a systematic
defect? And if he has identified a systematic defect, how is overall yield
affected by the mechanism responsible for that particular defect? Volume
diagnostics, in short, allow process engineers to rapidly identify the highest
pareto defect mechanisms prior to performing physical failure analysis. This is
a much faster and much more reliable way to identify the most critical yield
killing issues. During both new product ramp and the correction of process
excursions, root cause can now be identified in days rather than weeks.
Yield-analysis system
The architecture of the system developed by Synopsys and STMicroelectronics
is shown in Figure 1. TetraMAX ATPG scan patterns were used for the production
test screen and for diagnostics. In addition to the fault candidates from
TetraMAX diagnostics, the more traditional parametric measurement data from the
fab and bin sort data from test can also be loaded into the Synopsys Odyssey
Yield Management System for each failing device. Odyssey was also enhanced to
read and store key physical design attributes for each design in the new DFT
module. Once all this information is available for a sufficient number of
failing parts, the highest pareto fault candidates can be identified and those
can be easily correlated with either design features and/or process data to
drill down to root cause of failure.
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Figure 1. Yield-analysis system with TetraMAX Diagnostics and Odyssey.
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Analysis results
The first application of this system was a STMicroelectronics product vehicle
developed in a CMOS technology derivative. Several thousand die were tested from
many manufacturing lots spanning several months of time. Scan tests were applied
using a “continue-on-fail” methodology for all parts passing continuity and
gross leakage tests. This methodology provided an exhaustive set of test data
across two different operating conditions at VDDmax and VDDmin. The amount of
data collected was on the order of a few megabytes per tested die, which was
well within the memory available on the low-cost tester used for screening these
die. We now show three examples of how Odyssey was used to analyze the data
collected.
The chart in Figure 2 shows a pareto of cell candidates. The green part
of the bar represents the normalized cell fail rate at VDDmax, while the blue
portion is the normalized fail rate observed at VDDmin. Then specific cell
candidates selected from the chart are plotted on a XY bitmap to identify hot
spots by GDS location. These hot spots can be for a single die or composite die.
The analysis shown in Figure 3 was used to identify wafer-level failing
patterns. In this case, the objective is to identify any dependencies of cell
candidates by die location on the wafer. The stacked pareto chart shows the cell
fail candidates tested at VDDmin and displays the breakdown by “Stuck-At-0/1”
and “Slow-To-Rise/Fall” failure types. Individual maps may be selected from the
gallery for further analysis, or the entire set can be stacked into one
composite map to more easily identify the most frequently failing die positions.
Subsequent SEM imaging techniques can then be used to validate the actual
failure mechanisms at the specific fail locations (as shown in the die maps of
Figure 2).
The scatter plot in Figure 4 highlights the correlation between the number of
failing instances and the number of double vias in a particular net. This type
of chart was used to quickly highlight the most significant nets for early
failure analysis.
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Figure 4. Mining design physical attributes by failing
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Conclusion
This article shows the basic framework and initial results of a comprehensive
and flexible system for yield analysis using physical design data, process data
from the fab, production test data, and most importantly, failure candidates
from scan-based volume diagnostics. While each of these data types is useful in
and of itself, the ability to analyze and correlate production data across all
of these different domains enables a new and very powerful method to accelerate
yield learning. The system we have developed and the techniques we have shown
can quickly and reliably identify critical yield killing issues. This allows
shorter yield-learning cycles, ensure on-schedule delivery to target markets and
increases profits over the product life cycle.
By Cy Hay, Gary Green and Davide Appello. (Hay and Green are with
Synopsys, Inc., and Appello is with STMicroelectronics.)
Go to the Synopsys, Inc. website to learn more.
