January 9, 2008 -- The continual shrinking of IC transistor sizes and the market demand for systems-on-chip (SOC) solutions has resulted in more components on an IC along with larger die sizes. Designers are working with smaller device features connected over greater relative distances and more layers for the electronic signals to travel through than ever before. This presents a n unprecedented engineering challenge: creating circuits that are fast, accurate, and use less power in an environment where the circuit physics is far more complex and sensitive to variation, all while maintaining cost, timeliness, and throughput.
As advanced SOCs are pushing the technology envelope with higher clock frequencies, lower power supplies, and increased power consumption, the noise sources in these designs have increased but the high-frequency signals must still run reliably.
At 130-nm and larger process technologies, parasitic extraction can be done with tools that use simple cell characterization at the gate level and/or an assumptive method of measuring physical parameters. “Black box” methods and parameter measurement derived solely from drawn geometric information is sufficient at these nodes. At the 90-nm node, however, this methodology starts to break down. The difference between circuit simulation and silicon measurement has become significant, and more accurate techniques that look at advanced effects as well as process variation information are required.
In addition to the increased difficulty in achieving accurate parametric measurement, designers now have to perform numerous simulation tasks. In the past, timing was the main concern. Now, multiple extraction and simulation runs may be required for each area of analysis: power (R), noise (C), static timing (RC), dynamic timing (RCC), and signal integrity (RLC). Managing the data associated with these multiple requirements and analyzing the results is a significant time component in an IC design project.
Evolution of modeling (device and interconnect)
The standard paradigm in developing a circuit representation or “silicon model” of an IC has been to extract parameterized device models of the intentional devices (transistors, diodes, etc.) and integrate that with a calculation of the parasitics (resistance, inductance, and capacitance) associated with the interconnect. These two elements of the circuit were then integrated into an industry-standard netlist and sent downstream into simulation. To work within this paradigm, the entire industry has supported two distinct teams of experts: one to implement very accurate device models and another to develop methods for characterizing the interconnect.
As process technology has evolved, so has the sophistication of the modeling teams responsible for predicting circuit performance. Starting with the device models, the measurements required around a MOSFET have progressed from relatively rudimentary measurements restricted to a single device to very complex measurements that analyze the distance to the shallow trench, edges of the well, and device-to-device interaction (Figures 1a and 1b). These measurements must be extracted accurately and work in conjunction with industry-standard compact models to enable accurate device performance prediction.
Figure 1a. Left: Using RET (Reticle Enhancement Tools) capabilities, we are able to determine the differences between “as-drawn” and “as-built” geometries. Lithographic effects such as this happen at the die level and are very design dependent. Right: The silicon simulation results differ from circuit simulation of drawn geometries. This is because the “as-built” dimensions will perform differently and more closely match silicon.
Figure 1b. In a methodology for capturing three dimensions of variation information, litho simulation is done with LFD (Litho Friendly Design) to obtain a contour prediction of the silicon. Contours represent the x,y variation versus the drawn geometry. These contours are sent to convolution algorithms and then subsequent parameter extraction to obtain more accurate device and interconnect models. Similarly, to capture the z-direction variation, CMP simulators can predict thickness changes in the conductor which, again, can be captured by the parasitic extraction tool to achieve more accurate circuit simulation.
Smaller geometries (and spacings) also have required that the parasitic models must evolve. In the past, to get an accurate model of the interconnect, simple analysis of the “wires” was typically sufficient. Now, to be truly accurate, wires, vias, contacts, substrate, device-to-device, and even package effects must be captured to gain a realistic perspective of parasitic effects. In addition, because of the high frequency used in today’s designs, analysis of the magnetic field (parasitic inductance) must be incorporated into standard RC extraction flows.
Device and interconnect modeling (and their associated tools) now must be more closely synchronized than in the past. We are modeling a system, not just discrete parts of the whole, and modeling experts debate about which effects should be captured in the device model and what must be modeled as a parasitic.
On top of the increased modeling requirements, we also must deal with the fact that the printed silicon components do not match the drawn layout. This has led to discussions around modeling “as-drawn” and “as-built” effects. The variation is caused by both random and systematic effects, and the challenge we now have is to effectively incorporate this variation information into the device and interconnect models (Figures 2a and 2b), so that the as-drawn design will accurately reflect the as-built.
Figure 2a. Device parameters are layout-specific inputs to transistor models. The first generation of device parameters involved device size and shape considerations that change according to layout considerations such as multi-finger devices. The second generation of device parameters involved mobility considerations associated with trench and well mobility effects. Second generation device parameters still only consider individual devices. A third generation of advanced device parameters is being developed by foundries and IDMs to describe the interaction between multiple devices.
Figure 2b. Examples of measurements at the 45-nm node where device-to-device interactions are now taken into account.
In terms of systematic variation, the primary reasons for x,y variation of the device and interconnect dimensions are a result of the optical processing and etch effects. In the z-direction, the variation is primarily driven by the effects of CMP processing. All three dimensions of variation information need to be captured because changes in the dimensions of devices or conductors will have a profound effect on device and interconnect performance.
Initially, foundries provided tables of variation information derived from empirical measurements on test-chips. But at smaller process nodes, we are discovering that this variation can be highly context-dependent, and simulation methods are needed to inform the device and interconnect models.
The net result is that the foundry must now inform designers (and designers need to be cognizant) of how critical dimensions will vary so that effects can be compensated for in the design phase. Designers need to have the tools to effectively integrate “as-drawn” and “as-built” information into a comprehensive circuit model.
We are still left with the problem of random variation, and the implication is that we will still have to do corner modeling, albeit in a more intelligent fashion. Modeling as many as five interconnect corners is common on advanced processes. The interconnect corners include Cw (worst-case capacitance), Cb (best-case capacitance), RCb (best-case resistance and capacitance), and RCw (worst-case resistance and capacitance). Each corner is a different set of geometric dimensions (different models are built from the geometric data using different manufacturing process assumptions or conditions). In addition to that, there are typically three device corners. The implication for the designer is that, when including device and interconnect corners, 15 simulations are necessary to achieve coverage — and that is before considering temperature and voltage corners.
This is a daunting number of simulations, and when you consider the size of a typical SOC, it is no surprise to find that most designers do not have the time to simulate across all of these corners. What is required is a more efficient handling of this data.
Why should we have to exercise a parasitic extraction tool five times to get five netlists? Moreover, does it really make sense to simulate all permutations of possible corners? Is Cw with a fast device corner really possible? Or, if we are doing Monte Carlo simulation, does it make sense to truly vary all resistances and capacitances in an unrelated, yet statistical, fashion?
Parasitics can be correlated by physical parameters, and we know that if the process is going to vary on a metal line, capacitance may increase but resistance will decrease (or vice versa). Given this, an intelligent way to represent the parasitics would be to represent them as equations with sensitivity to the physical parameters (width, length, thickness, etc.) that affect their value. By so doing, we can achieve several improvements. First, we can achieve traditional corner flows much faster by exercising the parasitic tool once to derive any corner necessary (assuming a given corner is simply a finite delta value versus the typical corner, which is standard). This alone could speed up the parasitic extraction flow five times simply because you are reducing the number of extraction runs.
Secondly, and perhaps more important, this information can be presented to the simulator, and the simulator can now take advantage of this information to statistically vary the physical parameters that will affect both the device and interconnect performance. The advantage to this is that correlation between device and interconnect corners is transparent to the designer, and the result is a more efficient simulation with greater coverage (Figures 3a and 3b).
Figure 3a. Traditional corner management requires a single extraction calibration, extraction of the target design, and output netlist for each process corner desired. As the number of interconnect corners increase, 20 or more simulations is not unreasonable. To improve efficiency, sensitivity netlists that contain physical parameters and statistical simulation that access the physical parameters (instead of individual parasitics) can reduce the amount of time spent in simulation as well as improve overall coverage.
Figure 3b. In the previous example, the effort associated with multiple corner processing is so extreme that many designers end up using a single net list and Monte Carlo analysis as a second-best choice. This illustrates the difference in accuracy between Monte Carlo and the use of a sensitivity netlist. While Monte Carlo varies R and C values independently from the design and the interdependence on each other, the sensitivity netlist solution enables a more accurate description of circuit performance by ensuring each point is correlated with both physical process variation data and the effects that physical process variation have on a design performance. The result is a more accurate representation of the parametric performance.
No longer “business as usual”
We have described a perspective on how the industry has evolved from rudimentary modeling of rectilinear device and interconnect measurements in isolation to a more integrated system that accounts for both types of effects and incorporates what we know about process variation. The big question is what’s next?
The first step has been to correlate parasitics with the variations in physical parameters and apply this information to solving the traditional problems such as timing, signal integrity, IR drop, and electromigration. The next step is to apply this correlation and sensitivity information to situations that are not well-solved but demand accurate modeling — for example, to extract and simulate the true Ion, Ioff, or Vt. for a specific device and specific regions on the die. The ultimate goal is to then incorporate this into an integrated system that includes intelligent tools and accurate models with manufacturing and design expertise so that the design will be informed by all the relevant information. The process becomes transparent, with a high level of abstraction, and such a system will reduce the designer’s workload. All the designer will need to be concerned with is determining the best methodology for designing a clock tree or characterizing a VCO, etc.
By Carey Robertson
Carey Robertson is a Director of Product Marketing, Design to Silicon Division, Mentor Graphics Corp. where he oversees the marketing activities for layout versus schematic (LVS) and extraction products. He has been with Mentor Graphics for nine years in various product and technical marketing roles. Prior to Mentor Graphics, Carey was a design engineer at Digital Equipment Corp., working on microprocessor design. Carey holds a BS from Stanford University and an MS from UC Berkeley. He may be contacted at email@example.com.
Go to the Mentor Graphics Corp. website to learn more.