Page loading . . .

 Category: SOCcentral Feature Articles & Columns: Feature Articles: Monday, October 24, 2016
ESL Is Finally Ready for Prime Time  
 Printer friendly
 E-Mail Item URL

May 12, 2008 -- If you talk to vendors of electronic system-level (ESL) design tools, youíll find that many have a unique approach to this evolving technology. Some vendors talk of virtual platforms, others focus on synthesis and simulation, and still others tout design services that help engineers develop systems at a very high level of abstraction. Though ESL tool providers have different solutions, they seem to agree on a few essential facts. First of all, complexity is increasing rapidly, driven by shrinking silicon process nodes and multi-core systems. Second, software content is growing, which means that more than ever, software engineers need an abstract hardware model to begin writing code as early as possible. Finally, most everyone agrees that ESL will progress only after some standards are defined and made public, akin to the eventual stabilization of hardware description languages and other hardware design standards.

Though ESL has been around for years, itís only recently become a mainstream solution. Early adopters have been using various forms of ESL for a while, but the increasing complexity and software content of todayís systems are driving even small system vendors to consider adopting ESL techniques and tools.

"Everyone recognizes that the existing design flows are about as optimized as theyíre ever going to be," says Simon Napper, President and CEO of Synfora, a provider of algorithmic synthesis tools for SOC and FPGA design. "System complexity is increasing at a dramatic rate, which increases development costs that you canít easily pass on to consumers. Finding a new way of designing systems is a compelling reason to move to ESL. Moving to a higher level of abstraction has its benefits, but re-tooling your flow or spending time learning new methodologies isnít an option. A move to ESL, therefore, will be driven by establishing an implementation path from an abstract description (ANSI C) through to hardware that competes with todayís hand design in terms of power, performance and area." (Learn more about Synfora's view of ESL in the whitepaper Multimedia Application Specific Engine Design Using High Level Synthesis.)

Synforaís solutions take a C algorithm and a set of design parameters (clock frequency, throughput target, and technology files), and create a series of implementation models in RTL and SystemC. A compiler then exploits parallelism at multiple levels to find the most efficient implementation of the algorithm. A designer may also specify a range of design parameters and allow the tool to explore the implementation space. According to Synfora, its solutions then deliver efficient RTL that can readily be implemented with industry-standard physical-design tools. They also create testbenches for RTL, which recreate the C tests and verify that the behavior of the C and RTL are identical.

With product descriptions like that, it seems that ESL is a technology thatís ready for prime time, but many design engineers are wary of changing established flows. After all, the beleaguered engineer is constantly asked to balance the conflicting requirements of system performance, cost, power, silicon yield and time-to-market. Added to that, engineers must now look at their designs from a birdís-eye view to avoid downstream problems that could stall the timely release of the system. Faced with this dilemma, many engineers are tempted to stick with tried and true design flows.

"You could argue for keeping things as they are," says Marc Serughetti, Vice President of Marketing for CoWare, a supplier of platform-driven ESL design software and services. "But software developers and integration and test teams are asked to deliver better products faster with higher quality. But how can this be achieved when the hardware isn't available or is difficult to access, and the specifications are changing and the silicon design is unstable? In addition, the hardware platform includes heterogeneous multicores with complex interconnect, memory hierarchy and multiple dependent software stacks."

Figure 1. This screen shot of CoWareís virtual platform displays analysis and debug windows on the left. The ďrealĒ device is pictured in the upper right window. The lower right screen shows the device connected to its UART console.

So, according to ESL providers like CoWare, platform-driven electronic system-level ESL software and services will solve this laundry list of thorny problems. (Learn more by reading CoWare's whitepaper on Virtual Platforms for Software Development.)

Platforms to the rescue?

Often, engineers are leery of signing up for single-vendor solutions, and might want to shop around for an open platform that accepts models available from public sources. "We looked around and found several vendors with proprietary solutions for virtual platforms," says Simon Davidmann, founder and CEO of Imperas, a provider of ESL solutions for multi-core software development and debug. "Some develop a platform for your chip and you use that to develop your software, but theyíre proprietary, expensive and inefficient. At Imperas, we took a bold step and released our platform, which took three years and $4 million to develop, as an open virtual platform."

So, in March of this year, Imperas launched Open Virtual Platforms (OVP) to establish a common, open standard solution for developers to quickly and inexpensively simulate embedded software on SOC designs. The donation includes modeling technology, Imperasí existing library of models, and OVPSim, a reference simulator. Imperas will support and manage the OVP website, and will contribute much of its innovation to keep this infrastructure evolving.

"The goal is for engineers to have an OVP platform where they can develop their software," Davidmann continues. "The ground swell of initial support from EDA companies, end users and IP providers clearly demonstrates the need for revolutionary thinking in this area."

Though some engineers are intrigued by Imperasí open approach, theyíve decided to adopt proprietary ESL tools, knowing that if open standards evolve, they can always adapt to include them in their design flows. Some turn to established EDA vendors like Synopsys, which bolstered its ESL offering by acquiring Virtio and its Innovator virtual platform development solution. Some Synopsys customers have presented papers showing dramatic benefits from adopting ESL.

"At our usersí group in Israel, we had a customer say that it was able to develop virtual models 32 weeks prior to tapeout," says Frank Schirrmeister, Director of Product Marketing at Synopsys. "Because of that, the customer was able to start software development much earlier. We have other customers, such as Texas Instruments, who have seen the benefits of ESL and imported it into its design flows." (Make sure to also read Frank Schirrmeister's Executive Viewpoint on Standardization Opens Virtual Platforms to Mainstream Use.)

Figure 2. Shown here is the top-level of a virtual platform of Texas Instruments OMAP 2420 in its development environment. It was developed in Synopsys Innovator using transaction-level models and was instrumented with characterized power information. Several control and visualization elements are shown, including a software debugger attached to the OMAP 2420 ARM processor core executing the actual application software while providing associated power information. Various power related windows show the core voltage, the current voltage in the different power domains, a power dashboard for more detailed analysis, and a virtual representation of the actual test board.

The role of IP in ESL design

Almost every discussion with ESL tool vendors eventually comes around to the important role of third-party intellectual property (IP). After all, if the goal is to get a virtual system into the software engineers hands as soon as possible, thereís no better way than to use proven IP.

"No one designs an SOC from scratch," says Bill Neifert, co-founder and CTO of Carbon Design Systems. "70 to 80 percent of an SOC comes from previous designs. You must leverage the investment youíve made in your previous design and automatically create a virtual model that you can plug into your virtual prototype. That prototype is implementation-accurate because itís been generated from the previous system. As you refine your model or generate new IP, you have a path to integrate that into a virtual platform, so your software engineers are developing their code on the most accurate platform possible. Thatís our strategy when we develop our products."

Figure 3. Carbonís Model Studio GUI lets users manage a project, a library and the configuration of the design, with views of the design hierarchy and a source code browser. Its error report browser links to the source code.

Many companies rely on platforms that use an array of FPGAs running IP to play ďwhat ifĒ scenarios before a design progresses to final implementation. With that in mind, Synplicity, which made its mark with user-friendly FPGA synthesis tools, has established a foothold in the ESL arena.

"The time has come for FPGAs not just to prototype, but to implement complete systems," says Chris Eddington, Director of DSP Marketing at Synplicity. "We let users select, configure and assemble internal and third-party IP delivered in the IP-XACT format, integrate that IP, and then implement it into a variety of FPGAs, including those from Actel, Altera, Lattice Semiconductor and Xilinx. The new tool flow provides FPGA designers, using IP and system-level blocks, with an extremely productive path to implementing complex systems in FPGAs."

Moving on up

Some ESL tool providers move to even higher levels of abstraction, in an almost complete break with hardware design technologies and flows. These companies donít really have an EDA background or perspective, so they approach system design from a higher level.

"We model everything at an extremely high level of abstraction because we believe thatís where you get the highest performance," says Michel Genard, Vice President of Marketing at Virtutech, a provider of virtualized software development solutions for system-level design and development. "We look at ESL, not from a hardware perspective, as many ESL companies do, but from a software point of view. But we let users control time, add checkpoints and run any application forward or backward, similar to established hardware simulators. Our platforms also let software developers boot their platforms at the same speed as the finished system."

Figure 4. Virtutechís multi-board virtual platform analyzes simulation performance. The waveform gives a graphical representation of this analysis.

A formal approach

Some players in the ESL realm use technology that is an off-shoot of formal methods used in hardware design. Their solutions use equivalency checking techniques to ensure that a design stays in sync as it progresses from architectural description through implementation.

"We bridge the realms of system-level views and RTL," says Mitch Dale, Director of Product Marketing at Calypto. "Itís a formal method that uses high-level synthesis tools. In an ESL flow, we can verify that the synthesis results are identical to the original high-level code. Thatís important because there can be user errors, language ambiguities and bugs in the tools. We have numerous customers developing video compression and multi-media consumer devices like video cameras and cell phones. The big advantage is that they can adapt to new standards quickly. By writing at the system level, the software engineers can write code even as a spec is stabilizing and adapt to changes. These customers cite productivity increases anywhere from 10 to 20X." (Learn more by reading Calypto's whitepaper on Navigating the System to RTL Continuum.)

Some ESL providers increase productivity with products that focus on early hardware/ software verification and pre-software validation. They do this by letting customers build a virtual test environment instead of an in-circuit emulation (ICE) test bed. In this approach, they replace a set of speed bridges (Ethernet, PCI or USB) with an equivalent set of transactors. In general, an ICE test bed serves one specific design and isn't reusable on another. In contrast, transactors can be reused on any design.

"With a PCI transactor, for instance, it's possible to plug a PCI software driver to an emulated design with a PCI interface," says Lauro Rizzati, Vice President of Worldwide Marketing at EVE, a hardware/ software co-verification tool provider. "In addition, you can connect a software debugger to an emulator through a JTAG transactor and run in step-by-step mode. Designers change their whole verification perspective when they use transaction-based verification through a hardware-assisted platform. They get better results in less time and the whole experience is far less challenging."

Itís still a tough decision

With this broad range of technologies and approaches to ESL, it becomes hard for hardware and software engineers to choose an environment that will meet performance goals, control development costs, and meet time-to-market windows. But for an experienced engineer, thatís nothing new. Over the years, theyíve all committed to tools and techniques that ran the gamut from a spot-on solution to an absolute disaster. As with any consumer purchase (especially ones that cost in the six figure range), careful exploration of the vendorís claims and the actual project at hand must be considered.

ESL promises to save valuable time and preserve the original designerís intent. Thatís a heady statement, but one thing is clear. ESL has been waiting in the wings for some time now. Curtain up! Light the lights!

By Mike Donlin, Senior Editor,

Keywords: SOCcentral, electronic system level design, ESL, transaction level modeling, transaction-level modeling, TLM, ASIC design, EDA tools,
488/25664 5/12/2008 17751 17751
Add a comment or evaluation (anonymous postings will be deleted)

Designer's Mall

 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
and receive news, article, whitepaper, and product updates bi-weekly.


Verification Contortions

Dr. Lauro Rizzatti
Verification Consultant
Rizzatti, LLC

Real Talk

Drilling Down on the Internet of Things

Ramesh Dewangan
VP Product Strategy
Real Intent, Inc.

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
DSP Design
Analog Design
Digital Design
Mixed-Signal Design
RF Design
EDA Tool Development

IC Packaging
PCB Design
RTOS Development
RTL Design
SystemC Design
SystemVerilog Design
Verilog Design
VHDL Design

Post a Job
Only $100 for 30 days

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Design Center
Tutorials, Whitepapers & App Notes
Archived Webcasts


Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
553.488  0.078125