Page loading . . .

 Category: SOCcentral Feature Articles & Columns: Feature Articles: Friday, October 28, 2016
Manufacturing Concerns Move Up the Design Cycle   Featured
 Printer friendly
 E-Mail Item URL

September 2, 2008 -- The expression "design-for-manufacturing" (DFM) has been bandied about for so long, that designers regard it with suspicion. They've been told many times that shrinking process nodes will force them into a realm that was once happily reserved for the engineers at the fab who turn designs into working silicon. These warnings became especially shrill as designs approached the 90-nm mark. When the sky didn't fall at 90nm, DFM became known as "design-for-marketing" and many engineers continued their old, comfortable ways and simply tossed their designs over the wall and waited for a prototype.

In larger silicon houses, however, DFM was embraced at the 90-nm node because large companies have the engineering resources to adopt DFM methodologies and designers in those companies knew that DFM would eventually be a mandatory requirement. Today, even smaller companies are realizing that, like it or not, designers will soon be responsible for some level of DFM expertise, especially as smaller process nodes loom in the distance.

As these engineers begin to explore DFM technology, they're met with a dizzying array of definitions of the term. Just about every EDA company that has a product relating to the manufacturing process claims to have a DFM solution. Though these claims seem suspicious, there's some truth to them because DFM can mean different things to different EDA providers. Some companies produce intellectual property (IP) and libraries that have constructs in them that directly relate to the manufacturing process. Another DFM category applies to tools used post-layout to analyze, identify and help fix potential manufacturing defects at that stage of the design. Even standards organizations are jumping on the DFM bandwagon by proposing open communications protocols to ease communication between EDA vendors and fab engineers. Most mainstream EDA vendors, however, say that though these tools and techniques are useful, they aren't really the domain of the design engineer.

Additional Reading

The Shifting Landscape of DFM

A Comprehensive Approach to Manufacturing Variability

Systematic Yield Improvement Using BIST

Solving the DFM Interoperability Crisis

... But Will It Work?

"From Synopsys' perspective, DFM is used by designers who want to implement techniques that will lead to a successful tapeout and working prototype," says Saleem Haider, Senior Director of Marketing for the Physical Design and DFM Group at Synopsys, Inc. "These tools and techniques should be available at every stage of the design flow to give designers the information and EDA software they need to improve manufacturability. DFM must be incorporated into the tool set that designers are using, because trying to convince them to learn and use an array of tools outside of their usual flow simply won't work. Synopsys IC Compiler, which is a widely used physical implementation tool, features critical area analysis and optimization to improve manufacturability. We've also included via optimization, which is widely used today to reduce the number of vias as well as the number of isolated or single vias."

The latest addition to IC Compiler is a technology called Zroute. According to Synopsys, Zroute uses advanced routing algorithms and multi-threading capability to take full advantage of the newest multi-core computer platforms delivering 10X speedup with mainstream platforms. Zroute simultaneously considers the impact of manufacturing rules, timing and other design goals for improved manufacturability.

Figure 1. This illustration shows the various via layers of a design, with one region highlighted to provide a comparison between Synopsys' IC Compiler Zroute technology (right) and the current implementation (left). Vias can have an impact on the performance of a design, as well as on its manufacturability. Having fewer single vias also provides a better starting point for double-via insertion, resulting in a higher redundant via rate and improving manufacturability. As a result, customers report 10-15% fewer vias using Zroute.

DFM: A broad solution

Like Synopsys, most EDA vendors offer an array of tools that are DFM-aware and that are available throughout the design cycle. The hope is that by gradually adapting the design as it develops, the final GDSII file will be infused with design rules, honed by DFM technology and ready for manufacturing to prototype and produce in volume.

"DFM is not a single point fix," says Michael Buehler, Marketing Director, Design-to-Silicon Division at Mentor Graphics Corp. "There's not an obvious place for the designer to use DFM technology. It has to be considered at all phases of design. It can be useful even before the design process to establish rules at the outset of a project. For example, when engineers at a large company like Qualcomm prepare to adopt a new process node, they get the design rules from the foundry. They use DFM tools to do what-if scenarios to tune that design rule set to what they need for their proprietary design. They then go back to the foundry and give them the design rules that they need to use. That's DFM but it's not a traditional part of actual chip design. So DFM really starts with these trade-off analyses to tune the design and IP. The leading-edge companies are now using this method out of necessity after a few non-publicized train wrecks. DFM can be used as a competitive advantage and all the large companies know it." (Learn more about DFM and process variations by reading the article A Comprehensive Approach to Manufacturing Variability.)

Though DFM has been established at larger semiconductor companies, most engineers are getting their first taste of this technology when they venture into process nodes below 90nm. EDA vendors must, therefore, understand and integrate technology into their DFM tools and flows that incorporate intelligence and hard data from the manufacturing realm. This might be new even for some EDA vendors, who in the past didn't have to worry about manufacturing minutiae such as process variations and lithography technology. Rather than develop and adopt manufacturing rules for their tools, some EDA vendors acquire smaller companies that have been quietly working on their DFM technology. Regardless of whether an EDA company buys its way into DFM or develops it in house, one thing is clear. Every major EDA company must understand and integrate manufacturing knowledge into its tools.

"At Magma, we've incorporated DFM-aware features into our flows so that designers won't have to deal with technology that's new to them," says Doo Choi, Director of Business Development, Custom Design Business Unit at Magma Design Automation, Inc. "We consider lithography variation, deposition planarity and particle defects that cause systematic and random changes to designs at 90nm and below. Corrective changes to the layout are required to ensure that a design has no catastrophic failures. Running process modeling simulations in an implementation flow causes excessively long runtimes, and design processes never finish. Without marking the problem spots and making corrections, yield will degrade significantly. When our customers understand the consequences of not using DFM tools and techniques, they either adopt DFM or at least know that it's inevitable at lower process geometries. Still, today most DFM is used by high-volume and leading-edge fabless semiconductor companies."

Beyond traditional EDA

As noted at the beginning of this article, DFM technology doesn't just reside in tools developed by the EDA industry. It infiltrates other aspects of SOC design such as library development and layout optimization. According to proponents of these methods, incorporating data from the manufacturing facility into libraries and IP will make the layout process much smoother.

"Most complex SOC designs are not designed with cell libraries and IP blocks that are DFM-compliant or optical proximity processing (OPC)-friendly," says Tom Wong Vice President of Marketing at Takumi Technologies Corp. "Automated tools that enable this type of DFM-compliant layout are just beginning to appear, but they are becoming increasingly popular. Imagine using a flip-flop that is not DFM-friendly and this flip-flop is used 20,000 times in your SOC design. You now have multiplied your DFM problem 20,000 times. Wouldn't it be better to have a DFM-clean flip-flop to start with? The answer is pretty clear. It's not fun to have to repair 20,000 hot spots after a chip is placed and routed and the DFM checking tools then tells you that you have a problem."

"But producing DFM-compliant IP is not the job of the system designer," Wong continues, "it is the responsibility of the library and IP developer. For this to happen, the foundry has to be involved in providing the necessary tools and measurement metrics to form a baseline on what is DFM-friendly. Expect to see this trend being adopted in the near future, starting at 65nm and 45nm." (Learn more about DFM-compliant IP by reading the article The Shifting Landscape of DFM.)

Other companies are also using the manufactured chip to generate information that can be used in a DFM design flow. By analyzing a manufactured chip's corner case bugs and hot spots, these companies can develop information that's useful for IP developers and the downstream tools that use it.

"We provide software that generates IP based on test structures that are embedded in a device and used for manufacturing test," says Farhad Hyatt, Vice President of Marketing at LogicVision, Inc. "We use failure analysis to diagnose the problem, and with that information, develop IP that will correct those failures in the next generation of the chip.

"In memory, for example, we'll tell you which bits are failing and under what conditions they're failing. IP developers can take that information and modify the IO with increased spacing between metal lines, adding vias, or other techniques to improve manufacturability." (Learn more about using test structures for DFY by reading the article Systematic Yield Improvement Using BIST.)

Some peripheral issues

As noted at the beginning of this article, the term DFM spans a broad range of approaches and technologies. At Sigrity, for instance, DFM means analyzing what happens when the chip design goes into a package, which in turn, is placed on a circuit board. Failing to foresee the result of that interaction can result in system failure, even if the chip design, the package and the board are all functioning properly.

"People often design an SOC or ASIC in a vacuum," says Brad Brim, Product Marketing Manager at Sigrity, Inc. "They make some assumptions about how the whole system, including the package, is going to work. They don't take the load or driver for the chip into account. We extract package models and generate Spice models and send those to EDA companies who can use it to enhance their DFM technology. We call it chip-centric, package-aware design. If the whole system is considered when the chip is designed, chances are good that everything will work at final assembly." (Learn more about DFM and off-chip effects by reading the article ... But Will It Work?)

At the very edge of this DFM discussion is data transmission. After all of the rules have been followed and the chip is successfully designed, enormous design files must be sent to the fab. Some companies rely on tried-and-true but expensive ways to transmit data, namely using TCP/IP protocols or even CDs and couriers such as FedEx or UPS. Even with compression applied, the sheer size of a submicron design can make internet transmission prohibitively slow. Saratoga Data Systems has developed a data acceleration tool that allows files to be transferred in a fraction of the time of traditional technologies.

"We can send design files around the world 5-35 times faster than current methods," says Greg Fairbank President of Saratoga Data Systems. We have a data transmission tool called Flume, which accelerates IP communications without affecting data. In the beginning, we developed it for customers who wanted to send IP design files around the world. Now the EDA industry, fables semiconductor vendors and others are using it to send all sorts of files around the globe. A traditional solution to reducing file transfer times is to compress, where you might get a 75% compression rate, if you're lucky. But with today's enormous deep submicron process files, you're still looking at 100 to 250 GBytes of data to transmit. We cut that transmission time drastically without changing data. This lowers transmission costs, design time to market and preserves data security."

Figure 2. Long distance network data transmission is typically much slower than expected by users who have maximized their bandwidth within budget constraints. This is primarily due to the direct and indirect effects of latency - the time it takes for transmitted data to travel between a sender and receiver. In today's congested networks, current protocols seldom achieve more than a few percent of their theoretical channel capacity and, even worse, transmission sessions often fail altogether, demanding restarts. Source: Saratoga Data Systems.

Standards are key

One final aspect of DFM relates to a standardization of manufacturing data and GDSII files so that EDA companies, their customers and semiconductor fabs have a common path of communication. Though this isn't DFM itself, some proponents of standards say that without a common communication standard, DFM will have difficulty in becoming a widely used methodology. According to Si2, an organization dedicated to the establishment of standards, new information technology is necessary for the flow of both business and technical information across the supply chain to improve communication and boost efficiency.

"The vision of Si2's Design-for-Manufacturability (DFMC) Program is an open-standard IT infrastructure that will provide the means for enhanced communication of information across the IC supply chain and against which design and manufacturing applications can be integrated," says Jake Buurma, Vice President, Western Operations at Silicon Integration Initiative, Inc. (Si2). "This will provide a basis for more complete communication of information to improve design and manufacturing cycle times, more effective integration of the entire flow, choice of applications with less difficulty to insert them into the flow, and faster introduction of new design technology and transfer into production." (Learn more about DFMC by reading the article Solving the DFM Interoperability Crisis.)

The DFM era is finally here

Even with all of its facets and interpretations, most everyone agrees that process nodes under 90nm will force designers to use DFM tools and techniques. Even the most reluctant engineers know that process variations in deep submicron nodes will cause expensive and time-consuming respins if DFM rules aren't used at the outset of the design cycle. Designers who saw the writing on the wall at 90nm are already well versed in DFM techniques. Engineers who are slow to change, however, might be busy debugging numerous failed prototypes while their competitors ship working silicon out to market.

By Mike Donlin, Senior Editor,

Keywords: SOCcentral, design for manufacturing, design-for-manufacturing, DFM, design for yield, design-for-yield, DFY, FPGAs, field programmable gate arrays, ASICs, ASIC design, EDA tools,
488/26725 9/2/2008 13748 13748
Add a comment or evaluation (anonymous postings will be deleted)

Designer's Mall

 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
and receive news, article, whitepaper, and product updates bi-weekly.


Verification Contortions

Dr. Lauro Rizzatti
Verification Consultant
Rizzatti, LLC

Real Talk

Drilling Down on the Internet of Things

Ramesh Dewangan
VP Product Strategy
Real Intent, Inc.

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
DSP Design
Analog Design
Digital Design
Mixed-Signal Design
RF Design
EDA Tool Development

IC Packaging
PCB Design
RTOS Development
RTL Design
SystemC Design
SystemVerilog Design
Verilog Design
VHDL Design

Post a Job
Only $100 for 30 days

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Design Center
Tutorials, Whitepapers & App Notes
Archived Webcasts


Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
553.488  0.1875