September 2, 2008 -- The term design for manufacturability (DFM) means different things to different audiences. From a practical standpoint, DFM represents the communications between the design community and the manufacturing community to ensure that complex chips can be designed, verified and manufactured with short TAT and good yield. But each community has different priorities. Designers of complex SOCs working at advanced technology nodes (90/ 65/ 45/32nm) are primarily interested in translating system requirements into a circuit or a layout implementation that can be handed off to a fab or foundry. Engineering teams at manufacturers, on the other hand, are focused on how best to handle post place-and-route layouts to ensure that designs are manufacturable with predictable yield.

Historically, this communication takes place when a design is placed-and-routed and a timing-verified layout is checked against a set of design rules. If the layout passes this design rule check with no errors, then the designer's job is done. In some cases, some design rule violations can be waived when they are deemed harmless by both the design and manufacturing teams.

Figure 1. A typical system-on-chip design flow.

As technology moves to sub-wavelength, this simple design rule checking step is no longer sufficient to guarantee first pass success for silicon manufacturing. Lithography effects necessitate the application of optical proximity correction (OPC) to address litho effects and thereby maximize the chances of good silicon yield. This strategy is based on the premise that the OPC models are well calibrated and characterized, which is usually not the case in early silicon yield ramp for advanced process technologies. In order to avoid problems creeping up during the post place-and-route stage, designers are often asked to do more than just design rule checking before handing off a design to the manufacturing teams.

Figure 2. Comparison between a conventional design flow and a DFM design flow for sub-wavelength.

These issues spawned an entirely new EDA tool category as well as a number of EDA startups for DFM around 2002 DFM tools as a sector also gained substantial interest from venture capital communities and many companies were funded to explore all kinds of DFM concepts. Tools and products generally fall into categories aimed at distinctly different user groups with different usage models. These include integrated device manufacturers (IDMs), foundries, and fabless chip companies. However, the DFM problems that each of these constituents want to address are completely different. IDMs focus on manufacturing and yield and generally need tools to help them achieve a faster yield ramp. Foundries also want faster yield ramp, but need to supply all the information their customers require to deliver a high quality and highly manufacturable design to the foundry. Fabless chip companies focus on quick turn around time and first time success for their system-on-chip (SOC) silicon. They will do what the foundries require. They view DFM as substantially a foundry's responsibility and expect the foundries to provide whatever data, rules, flows, tools and guidelines that are necessary to achieve first time success.

IDMs offer everything under one roof. They own the chip and IP design teams, the process, design rules, SPICE models, litho models, OPC models and have all the information and feedback they need from the fab itself. This closed loop co-ordination allows the IDMs to start DFM implementation and deployment ahead of major foundries and fabless companies. Since IDMs' main business was to build high volume SOC chips to support their internal vertical business or to provide high volume chips to consumer companies as well as networking industry, they have adopted the more advanced technology nodes first. This reality forced them to adopt DFM techniques earlier than others in the chip industry. Since 2002, IDMs have adopted both model-based as well as rule-based DFM techniques in areas of critical area analysis, litho hot spot detection including automated hot spot fixing for full chip layout, as well as multi-property layout analysis and optimization.

Some DFM companies have developed incremental OPC tools, faster lithography simulators, hardware accelerated litho simulation, hot spot detection tools, critical area analysis tools, advanced 2-D compaction tools, CMP modeling and inverse-lithography tools. Others have developed eDFM solutions to address the specific needs of their user base by providing design flows that streamline OPC processing via criticality analysis, improve OPC to reduce flash counts for efficient mask making, analyze GDS layouts and perform layout optimization to build DFM-compliant and litho-compliant libraries and IPs.

Figure 3. The shifting landscape of DFM.

Foundries have opted for rule-based solutions to address yield ramp. For each potential yield ramp issue identified in the fab, new design rules are written to prevent such things from happening. In addition to mandatory design rules, designers are now starting to implement DFM-rules or recommended rules as well, especially in 65 nm and 45 nm processes. However, the relative importance of each recommended rule varies from design to design. Some rules are more important in layouts that use mostly logic gates, while other rules are more important in layouts that rely more heavily on memory structures. Tools that can perform priority-based automatic enforcement of recommended rules will remove the barrier to widespread adoption of recommended rules for sub-wavelength designs.

Around 2006, DFM finally got the attention of the large EDA companies. To catch up to their smaller competitors, the big EDA firms placed a number of strategic investments in smaller firms and in some cases acquired some early start ups. So the consolidation of DFM companies and the weeding out process has already begun.

At the same time, some in the DFM industry believe its initial segmentation may be wrong. The market cannot be divided cleanly into IDMs, foundries and fabless companies. The industry may have to look at user behavior and user responsibilities to determine which DFM tools and solutions should be deployed, at what stage in the flow, and by whom. There have been serious efforts to develop manufacturing-side DFM tools such as CAA modeling to address effects of random defects, litho simulation to manage printability, improved OPC tools to better cope with accuracy and data sizes, and automatic hot spot mitigation tools through layout optimization.

Major investment has been allocated to design-side DFM tools as well. These efforts have attempted to move DFM into the designer's tool chest to give the designer the ability to eliminate potential manufacturing issues early in the design cycle. It has been generally acknowledged that trying to fix major DFM issues after a design is "placed and routed" and "timing-verified" is highly expensive and should be used only if other solutions do not exist. The industry also recognizes that DFM is a system level issue and should be viewed as such.

It is impossible to have DFM-clean designs at full chip level if you start out with a non-DFM compliant cell library or non-compliant IP blocks. Many DFM tools now focus on ensuring that all the building blocks in a designer's tool chest are DFM-compliant so that once a SOC chip is finally assembled, DFM corrections are minimized.

Another way to look at DFM tools is to segment the issues into two different categories. The first category is critical layer (metal1/poly/via/diffusion). The second is layers above metal 1. Clearly the first category is meant for cell library, custom cells and IP blocks including I/O, memory and analog. The second category encompasses full chip issues that can be mitigated by DFM-aware place-and-route tools. Thus far, we have seen companies providing specialized tools for both segments.

Recently efforts have begun to define DFM measurement metrics or DFM scoring for advanced cell libraries and IPs. A DFM-ecosystem has to be developed to ensure that full chip SOC designs do not start out with non-DFM compliant building blocks. As DFM technology has matured, the industry has also recognized that DFM issues are best addressed in different parts of the chip design flow depending on the nature of the problem. For example, full chip random defect issues and CMP problems are more easily resolved by place-and-route tools. On the other hand OPC or hot spot fixing tools offer significant advantages when addressing printability problems. And DFM issues in critical layers such as metal1/via/poly should be resolved at the cell or IP stage rather than wait until the problems surface at full chip level. Currently, just about every major IDM and library provider is evaluating the benefits and tradeoffs in adopting RDR (restricted design rules) for 32 nm as well as implications of double patterning.

Clearly the DFM industry has evolved dramatically over the past few years. As designers and manufacturers have moved down the process curve, they have gradually realized the key role DFM tools play in the development of successful first pass silicon. By moving these new capabilities up in the development flow, the rapidly changing DFM landscape promises exciting new opportunities to address the imposing design and manufacturing challenges posed by deep sub-micron process technology.

By Tom Wong.

Tom Wong is Vice President of Marketing, Takumi Technologies.