October 28, 2008 -- The addition of test structures, whether they're scan chains or built-in test circuitry for at-speed testing of fabricated designs, means additional steps need to be taken in the IC design stage to ensure correct operation of the final part. This further complicates the timing sign-off cycles for IC designers. In practice, this becomes another design mode that needs to be considered.

Additional modes could include various power settings such as full-frequency, low-battery, and standby. Besides design modes, all the different corners of the standard cell library need to be considered with a mixture of slow and fast devices. In speaking with a person at one semiconductor company recently, we discovered that they had a design with 14 modes and 16 different corners. This means that over 200 runs needed to be completed. Obviously, any method or technique that will allow teams to do those multiple corners and runs would provide a significant advantage to design teams, as they go through the find-and-fix timing closure loop.

Figure 1. Traditional corner-based timing analysis predicts circuit performance on a mix of slow (S) and fast (F) devices.

To achieve fast timing closure, particularly in the presence of post-layout signal integrity effects that can dramatically slow analysis, a new kind of timing analysis is needed. Multi-threaded timing analyzers such as GoldTime from Extreme achieve over 5X faster performance with a significantly smaller memory footprint because of new algorithms. This new approach is essential for design teams that want to analyze 10 to 50 million cell instance designs in hours rather than days. Multi-dimensional optimizations of designs across modes and corners can now be done practically for even the largest designs.

Figure 2. Statistical timing analysis predicts circuit performance across all process (P), voltage (V) and temperature (T) variations in one analysis.

Improving design-for-manufacturability

One approach for improving the robustness of designs so that they are less sensitive to manufacturing and environmental variations is to use standard cells that are relatively insensitive to these kinds of effects, yet deliver the desired performance. Statistical analysis techniques can be used to analyze the sensitivity of digital cells in a standard cell library and create a statistically-aware cell library. By using statistical timing analysis with this enhanced cell library, the impact of manufacturing variations can be considered. Engineers can see ahead of time which paths and portions of the design are particularly sensitive and can swap in more robust cells to improve yield of the final parts.

By Graham Bell

Graham Bell is Director of Marketing for Extreme DA