In late November, Altera increased its guidance for the Q4CY09 to a quarterly increase of between 15% and 18%, which is very high by historical standards.
The FPGA market is dominated by Xilinx and Altera. The two companies compete across a wide spectrum of the available market, but completely dominate the lucrative high-performance sector. They are joined at the cost-sensitive end by smaller players such as Lattice, Actel and QuickLogic. New market entrants Achronix, SiliconBlue and XMOS have started shipping products and their strategies and market positioning are analyzed in "The FPGA Market Report" prepared and published by High Tech Marketing. All the participants are fabless semiconductor companies.
Many other companies have tried and failed to participate in this market. These include start-ups and large established companies such as Intel, Motorola and Toshiba. The FPGA market makes demands on the silicon, software and customer support areas that mark it out as difficult to penetrate.
Of greater concern is the apparent inability of the PLD sector to break through the $4B barrier. The growth of both Altera and Xilinx was outpacing the overall semiconductor industry up until the recession in 2000. Having experienced revenue reductions of up to 50% during 2001, they have clawed back to similar revenues, but not matched the revenue growth of the 90s.
FPGA vendors maintain that they can grow their revenue by making inroads into other segments such as ASSPs and DSP. However, this is not straightforward and may not always result in increased revenue.
The industry has grown partly because each new product generation passes on the benefits from Moore’s Law in the form of lower prices or more logic for the same money. Paradoxically, this means that FPGA companies have to either sell more devices in total, or devices with significantly more logic to get the same revenue. This is not the whole picture because the customer base is steadily increasing, and so is the usage within each customer.
FPGA use grew from logic consolidation, through small and medium volumes, and now the devices often form a key part of the system. The impetus to use programmable devices rather than adopt a customized solution was often to gain a time-to-market advantage over competitors. Today, many customers use programmable solutions, but the design time advantages have been built into the ever-contracting design cycles. For most companies, the gain is to get to functioning hardware earlier than would otherwise be possible. The system integration and debug times still mean that the production does not start until several quarters after the FPGA design is complete. As system complexity increases, the task becomes more difficult. The use of FPGAs can assist in contracting overall time scales, because the hardware platform can sometimes be modified to assist the design team to meet the overall requirement. An example is where a software routine does not complete fast enough, so a hardware accelerator block can be fitted into the FPGA to off-load the software.
The technological driving force behind FPGAs over the last decade has been the regular process enhancement that is commonly called Moore’s Law. In fact, it is not strictly a law of nature, but just happened to predict with striking accuracy how innovations and "work arounds" would continuously manage to push back the boundaries of the possible. The benefits from this development are very well documented, and are normally associated with processors, memory and very high-volume applications such as handset chip sets. What is also common knowledge is that the cost of producing new devices using the latest processes has escalated to multi-millions of dollars once the tooling and engineering expenses are totaled.
It is not always appreciated that FPGAs are one of the few product categories to fully enjoy the benefits of Moore’s Law. This is because the FPGA vendors can amortize the high costs over a wide customer base to reduce their risk and exposure to a single customer or market segment. They can also utilize the substantial increase in available transistors by offering more programmable logic, a greater quantity of user memory and substantial hard macros such as PCI Express interfaces in their high performance families. For these reasons, Altera and Xilinx have aggressively pursued leading-edge technology, which has the additional effect of raising the barrier to entry for all competitors.
Previous process shrinks had enjoyed the "win/win/win" benefit of lower cost, faster performance and lower power compared to earlier technology. Below 90-nm, the Moore’s Law rules changed to something closer to select any-two-from-three. The smaller die would always give lower costs, but increasing performance normally resulted in the same or possibly higher power consumption.
The complexity of FPGAs has risen in line with Moore’s Law. This provides approximately a doubling of density at each new process node. The result is that in 1998 the leading edge products from Altera (10k family) and Xilinx (Virtex) both used a 220-nm process and provided a total of 12k and 24k LEs respectively. Today, the equivalent densities using 40-nm processes are 820k and 760k LEs. Customers have seen an increase in available logic of around 34X over the period, in addition to an increase in performance. The increase mirrors the packing density (2202/402 = 30) as was predicted by Moore’s Law.
Figure 1. Largest FPGA announced (by equivalent 4-input Logic Elements - LEs).
Comparison of high-performance FPGAs
This market segment is exclusively the province of Altera (Stratix families) and Xilinx (Virtex). Two of the recent entrants, Abound Logic with its Raptor family and Achronix with the Speedster products are attempting to penetrate this segment. Each family member is represented in these figures to provide a visual indication of the breadth of the product range.
Figure 2. Logic element count for high performance families
An analysis of the end-user markets provides a picture of the overall PLD market shipments. Vendors report sales in approximately similar categories.
Figure 3. PLD market by end applications Q3CY09.
ASIC, ASSP and DSP market overlap with the FPGA space
These sectors are where Altera and Xilinx believe they can grow their revenue faster than the overall semiconductor market. It makes the assumption that the customer chooses a replacement strategy, rather than using the FPGA as a companion chip to add features or off-load processors. In many cases an FPGA will be included to provide other functions, and the new uses will be incorporated into the device.
The DSP processor is estimated to be worth $5.3B by Databeans, and to be growing at 11%. The majority (70%) is from the communications market, and is dominated by mobile phones where FPGAs cannot participate. FPGAs are often used as companion chips to provide the "heavy lifting" for DSP processors. The synergistic relationship does not allow the FPGA to replace the DSP processor, because FPGAs are less efficient at the data movements where the processors excel. Other applications such as consumer video and industrial imaging are examples where an FPGA can occupy a socket where a DSP processor might otherwise be used.
ASSP devices are typically dedicated to a specific market and reflect in-depth knowledge of the requirements and specifications. They are often created using an approach similar to an ASIC and are, therefore, efficient in their use of silicon reflected in an aggressive price. A limitation of an ASSP for the user is that all the competitors can use them to produce products with similar feature sets. Replacing an ASSP device requires that there is IP available for the FPGA either from in-house or via a third party. The customer can then license the IP and port it into an FPGA. This only makes commercial sense if the final solution has a lower total cost than the ASSP when totaling the FPGA price, plus any IP license fee together with the additional engineering costs associated with incorporating the IP into the solution. It does provide the opportunity for customers to incorporate their own features into their end products, and this is often the stimulus for adopting this approach.
Gartner forecast that application-specific standard product (ASSP) will reach $57.2 billion in 2009. This is one of the key target areas for Altera and Xilinx to gain greater penetration and break out beyond the $4B total market barrier. Naturally, the incumbent vendors will defend their patch.
By Paul Dillien
Paul Dillien founded the high-technology marketing consultancy company High Tech Marketing. He has worked in the semiconductor industry for over 30 years, including various Sales and Marketing roles working for Xilinx, Plessey and Ferranti.
Go to the High Tech Marketing website to learn more.