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 Category: SOCcentral Feature Articles & Columns: Feature Articles: Thursday, November 27, 2014
The New Standard for 32-nm IC Physical Design and Signoff  
Contributor: Mentor Graphics Corp.
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March 11, 2010 -- With the advent of advanced process nodes, IC design teams have an increasing ability to pack more functionality and performance into state-of-the art SOCs. However, design challenges are growing as we push the limits of complexity, size, power reduction, and manufacturing scaling. Designers need a new generation of physical design tools to effectively address these issues. Starting at 45/40nm, the increasing complexity of DRC and DFM rules began to stress traditional physical design flows. This trend is expected to continue and worsen at the 32-nm and 22-nm nodes, where manufacturing closure may become a serious bottleneck in design schedules.

Increasing difficulty of manufacturing signoff

The source of the growing manufacturing signoff challenge is the widening gap between manufacturing and design. Features get smaller, but the resolution attained through 193-nm light lithography stays the same, which introduces significant variations in line width, thickness, etc, that affect the yield and performance of ICs. Addressing this process-design gap the gap between shrinking feature size and constant lithography resolution is the fundamental reason for the numerous and complex design rules at the advanced nodes.

Figure 1. The gap between the wavelength of light used for lithography and the feature resolution required. This gap is responsible for the growing number and complexity of design and manufacturing rules that the design must adhere to.


The number of DRC/ DFM rules for 32nm has easily doubled since the 90-nm node, and the rule complexity, measured by the number of operations required to verify the rules, has grown even faster (See Figure 2).

Figure 2. The number of design rules, and the complexity of the rules, has risen steadily at each process node, leading to growing problems in design closure.


Typically, during physical implementation, place and route tools use simplified DRC/ DFM models to provide the optimal trade-off between runtime and accuracy. Once the implementation is complete, the GDSII layout is verified using signoff quality DRC/ DFM models. At previous design nodes, this traditional flow was sufficient, but the rules at 32nm are so complex that some cannot be effectively defined for physical implementation tools. In addition, the growing use of IP has exacerbated the problems because of outdated rules or mismatches between the abstracted cell layout view used in place and route and the complete GDS view used in signoff.

This disconnect between the implementation and physical verification has caused the number of DRC and DFM errors to increase significantly during signoff. The result is a time consuming cycle of multiple, non-convergent iterations between verification and physical design in order to achieve physical signoff.

Further, the DFM analysis and enhancements including metal fill/ CMP, litho, and critical area analysis are now starting to affect the traditional design metrics such as timing, power and signal integrity. This means that DFM effects need to be accounted for early in the design flow with full context of the design constraints. Going into 22nm and beyond, this problem will get even more severe as the limitations in light lithography require more design corrections to account for the variability between the "as-drawn" and "as-built" shapes.

The design-then-verify flow that has worked in the past is increasingly getting unmanageable and unpredictable. The result is delayed time to market and wasted engineering resources.

Designers need new tools to enable signoff manufacturing closure during physical design for a true correct-by-construction approach. This requirement sets a new standard for IC design flows to help designers meet tight constraints for DRC and DFM, and ensure better design quality and faster time to closure.

The case for golden physical signoff within place and route

For a timely and predictable design closure, we must avoid DRC/ DFM surprises during signoff. Iterating late in the design cycle is very expensive and could lead to missed market opportunities or low yields. To achieve this, the place and route tools must be able to use the signoff quality models during design and take appropriate corrective steps for potential violations. This includes the ability to use the foundry models expressed in the golden standard verification rules format (SVRF) within the place and route environment. In addition to flagging potential violations, such a design system will allow DRC/ DFM repairs to be made in the full context of timing, power, and signal integrity. It would also nearly eliminate the time-consuming data transfer between implementation and sign-off verification tools (See Figure 3).

Figure 3. The traditional flow on the left requires multiple iterations between the signoff and design environments for finding, then manually fixing errors and performing enhancements for manufacturability. Flow, on the right, would incorporate physical signoff capabilities within place and route.


As the industry is moving towards the next generation of manufacturing closure solutions, it is important to ask yourself the following questions:

  • Is the place and route tool being driven by the true golden signoff models and engines? If not, late stage surprises can still occur, leading to painful iterations.
  • Does the place and route tool have the capability to truly prevent and repair the signoff violations in an automated fashion?
  • Does the solution offer a complete and comprehensive DRC and DFM suite?
  • Can manufacturing closure be achieved in a holistic fashion without affecting the traditional design metrics like timing and power?

Benefits of DFM prevention within place and route

To improve manufacturing signoff, more detailed models are needed earlier in the flow. Place and route tools need to take advantage of advanced modeling techniques like equation-based design rules measured against three-dimensional (3D) "as manufactured" geometries for both devices and interconnects. Straightforward layout enhancements during place and route, such as wire spreading, metal fill, and via doubling are useful, but for upcoming process node designs, implementation should also include more sophisticated DFM layout optimizations to ensure accurate timing, power, and signal integrity closure while also improving manufacturability.

Lightweight models for critical area analysis (CAA), litho process checking (LPC), and 3D variability (or planarity) analysis should be concurrently handled along with the routing rules. This would help to prevent "litho-unfriendly" patterns from being created in the first place, and to drive global and intelligent wire spreading, widening and metal fill as the layout is being constructed, rather than as "after-the-fact" fixes.

Besides making the physical signoff process more manageable, advanced DFM optimization during design has other inherent advantages. For example, the design tool knows which paths are the most critical for timing, so it can take special care to minimize parasitic variations when doing metal fill or optimizing "white space" around these paths. The challenges of upcoming process nodes are severe enough to warrant significant improvements to the traditional design-then-verify flow. New EDA solutions are needed to minimize the growing gap between design and signoff in order to maintain competitive time to market, reduce development cost and effort, and boost profitability.

By Sudhakar Jilla.

Sudhakar Jilla is the marketing director for place and route products at Mentor Graphics Corp.. Over the past 15 years, he has held various application engineering, marketing, and management roles in the EDA industry. He has been previously responsible for the rollout of several market leading products and initiatives such as Pinnacle, Olympus-SoC, Design-for-Variability at Sierra Design Automation and Physical Compiler, Galaxy-SI at Synopsys. He holds a Bachelors degree in Electronics and Communications from University of Mysore, a Masters degree in Electrical Engineering from the University of Hawaii, and a MBA from the Leavey School of Business, Santa Clara University.

Go to the Mentor Graphics Corp. website to learn more.

Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, place and route, place-and-route, placement and routing, design for manufacturing, design-for-manufacturing, DFM, SOCcentral, Mentor Graphics,
488/30894 3/11/2010 6907 6907
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