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 Category: SOCcentral Feature Articles & Columns: Feature Articles: Wednesday, April 23, 2014
A Look at ESL  
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SOCcentral sat down with Simon Bloch, Vice President and General Manager of Mentor Graphics Design and Synthesis Division to discuss some of the conflicting definitions of what ESL really is, what Mentor Graphics is doing in ESL, what technology still has to be developed, and where the entire market is going.

Bloch: I would give a brief definition of ESL based on one of the two approaches. One is based on function and one is based on task. Based on the functional definition of ESL, itís really a TLM-based (transaction level model-based) platform that accommodates three major functions ó verification, synthesis and design ó very similar to what we have done in RTL. You can put all the functional tools of RTL into those three categoriesóverification, synthesis, designóand so it is for ESL. ESL is just a higher level of abstraction, so instead of dealing with signals and bits, like in RTL, we're dealing with transactions.

Whatís the difference?

The difference is that if you have a 64-bit bus, for example, instead of saying exactly that the control logic does whatever it does ó that is, how each of the bits operates ó in TLM we say that when certain conditions are met, that a transaction equivalent to transfer of data from A to B or for a read function from point A to B is occurring. Just higher level, faster, not containing all the details, but at that level they are not really needed or necessary. So thatís one view of ESL based on function which is very equivalent to RTL.

But in the end, we deal with users and users have certain responsibilities and do certain tasks. So another way to look at ESL is by task. We identified four major tasks that can be done on this TLM platform since we said ESL is TLM. One task is hardware design that's done by engineers concerned with architecture. One of their tasks is to analyze and optimize architectures.

What does it mean to optimize architectures? Optimizing means that even if you have all your components in the design defined, connecting them in different ways results in different throughputs. For example, if you have an interrupt controller connecting directly to memory versus connecting through some arbitrator, it results in a different response time to the interrupt and the choice is part of the architectural decision. These decisions are driven by different requirements. Sometimes you need response time, sometimes there are power considerations, sometimes there are throughput considerations; but thatís part of architectural thinking and decision-making. So as part of the architectural design, you analyze designs for those intents and purposes, which means power, performance, and area and you make adjustments. You analyze them and change them until youíre happy with the trade-offs that you've achieved. Thatís architectural design, and thatís first task.

The next task, once the architecture is performing the function that the designer wants to perform, is to incorporate software. This task is virtual prototyping and it's usually done by software designers. Virtual prototyping means running and debugging the software against the type of platform that's been designed. So virtual prototyping is the second task.

SOCcentral: Donít some people define virtual prototyping as basically running the hardware independently on some sort of emulation system or the equivalent?

Bloch: Thatís just hardware prototyping. Virtual prototyping means that no hardware exists and you're modeling everything. Everything is virtual and there's no hardware involved. Itís all models. But Iíll touch on hardware prototyping in a moment.

The TLM platform that you build is all virtual. Itís all modeled in software and once you think the hardware is final, you wrap it in a virtual prototyping package and give it to the software people. Now software people can run the software, debug it, analyze it, and change it on the virtual prototype . It might happen that to achieve the desired system performance, or power, or area, making changes on the software side aren't sufficient. So you need to go back and change the hardware architecture and that goes back to architectural design, and hardware design and virtual prototyping interact with each other. Thatís why our product Vista is actually a combination of both. It can be used for architectural design functions by hardware people and for software analysis functions as a virtual prototype by software people. Vista can do both in terms of taking software and hardware into account to accommodate hardware and software designers.

The third task is functional system-level verification and some people do this strictly on the TLM level because itís fast. Thatís where a derivative of it is used in hardware prototyping, and this primarily applies when you already have a sub-block of the design. If itís an IP that you're re-using, why do you need to virtually prototype it when you already have the real hardware? So thatís where the idea comes in that if you already have a part, why donít you run it fast on some hardware accelerator so that it can connect to the TLM environment and still provide the speed that you expect for the TLM level, but your using real hardware?

This approach has limits if things donít work. Itís very hard to debug real hardware and that was always the case with FPGA prototypes. They run fast real-time and if they give you the right answer itís good, but if they donít give you the right answer, debug is quite difficult.

So thatís the third task. The first task I said is architectural design and the second is virtual prototyping. The third piece is system-level verification, all based on TLM platform. And the fourth task is high-level synthesis. That's implementation.

High-level synthesis does not necessarily work off TLM platform but it creates TLM platform because high-level synthesis today is more intended to be used at C synthesis and it can produce TLM that can be plugged in as part of the system environment and once itís verified, it can produce RTL for implementation.

So to summarize my long answer, from the task perspective of ESL, which is TLM-based design, itís architectural design, virtual prototyping, system-level verification, and high-level synthesis. These are the four tasks that are driving ESL.

SOCcentral: What do you see as the next step Mentor Graphics in developing your ESL tools and your ESL concepts?

Bloch: I still think we are at the beginning of the road for ESL, in general. Itís not virgin, meaning no usage, but developing. From what Iíve seen, virtually every company in the semiconductor and systems space is using some parts of ESL today. It could be on the high-level synthesis side, it could be on the system level, verification, or as we mentioned, virtual prototyping. Each of them start deploying one or another piece based on the application segment and the pain that exists in that application segment.

For example, the wireless segment is more sensitive to algorithms. So I would say that they are the first to deploy high-level synthesis approaches.

The automotive segment, on the other hand, is much more sensitive to running software on processors. There's some architectural design, but really the mapping of architecture to software is the most critical. So they started with virtual prototyping.

Some consumer products, such as cable modems, are much more sensitive to system-level verification because they incorporate pieces of new code but there's also a lot of reuse. So every company today, deploys some piece of ESL.

The challenge is to have all of these segments deploy more of the same, meaning more users using the same and then expanding into other areas of ESL, which includes the other tasks. Or if they started from verification, expanding into design. If they started from synthesis, expanding into design or verification as well.

Mentor sees its role is in this usage as two-fold. For one, each individual product line needs to be best-in-class. Synthesis was started a number of years ago and initially it was good for certain application segments such as wireless. We added video functionality. We added control logic functionality, so itís actually expanding into applicability of design. So I think making it better in terms of quality-of-results and usability, so each individual product line needs to be best-in-class. So thatís one of role, and thatís true for our Vista product as well.

SOCcentral: The term ESL is used very freely by smaller companies which have only bits of this. Where do you see these companies going or how they might survive two, three or four years down the road?

Bloch: Smaller companies, as in the past, as in any EDA area, are focusing more on point solutions. They identify a problem and, hopefully, itís a big problem. If they find a good solution, they can promote it as part of a larger flow and then hope to grow organically and expand into an even bigger flow, or be acquired. I still think that smaller companies can innovate in the point solution space.

For example, formal verification is a very painful area. For example, ESL-to-RTL formal verification. There is a company, Calypto, that does some of that. There is probably room for additional technological expansion. Thereís a lot of small companies that participate in high-level synthesis..

SOCcentral: Who are some of the players among the smaller companies?

Bloch: Our number two market-share holder in high-level synthesis is Forte Design Systems. Gary Smith has identified a number of others like AutoESL and Bluespec. But, as Gary points out, the high-level synthesis tool of the future needs to incorporate aspects of algorithmic design, control logic design and communications layer design, and the company thatís going to provide it in the best environment is going to win that game.

So high-level synthesis is a sub-market on its own within ESL. I definitely think small companies can play here, as is Mentor. Within Mentor we are investing in each individual product area but more and more we are investing into connecting these tools with one another as well putting them in a flow such as Vista, where we have shown that Vista is now also working with Catapult, trading information back and forth. Thatís what customers are asking us for.

SOCcentral: Besides the cost involved, what do you see as the major barrier to organizations adopting ESL technology?

Bloch: I think the major barrier is resistance to change. My observation about companies that successfully adopted these new ESL technologies, whatever it may be, high-level synthesis or verification or architectural exploration, itís management taking an active role in asking ó not forcing, but asking ó and working with their people in adopting those new technologies.

For example, I had an experience with a director-level manager of a cable modem chip-design team. He managed a design team of about 50 people where they basically said that they could do better handwriting RTL as opposed to moving into the high-level synthesis space. The manager, who was quite technical, was able to have a technical discussion with his people, and his question to them was "how long would it take them, and what kind of area penalty they would suffer, using high-level synthesis"? The design team answered that the area penalty might be 10 to 15%. The manager just made the decision and said, "I donít care if handwritten RTL is going to be smaller by 10 or 15%; if ESL will let you do it three or four times faster, well Ö"

SOCcentral: If I were an engineering manager, I'd buy the 10% area penalty if I could reduce the time it takes by factors of 2 or 3!

Bloch:Exactly. That was a management decision, but the guy was still technical enough to be able to make that kind of assessment and ask his people to buy in. Managers that are less tied-in, more removed from the engineering teams, and enable their engineering teams to make all the decisions, usually those engineering teamsÖ You know, engineers invent, but they are conservative people.

SOCcentral: Any other observations youíd like to comment on?

Bloch: ESL is one of the exciting areas of EDA, for me personally. I think this is going to be a significant segment of design. I think the way things are going now ó with more algorithmic content being added and more software content being added and more system content being added to the designs ó there's no way that semiconductor companies can differentiate on process technology.

We're moving to fewer fabs or fewer process. There are literally two camps of fabs today, whether the IBM alliance or the TSMC alliance. Chips need to be done, so they are going to be done one way or another. They are going to be done and implemented and manufactured, so how do companies differentiate? The only way they can differentiate is based on the system content they put on the chips and thatís what, in my opinion, ESL is providing the ability to achieve.


Simon Bloch

Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, electronic system level design, ESL, transaction level modeling, transaction-level modeling, TLM, SOCcentral, Mentor Graphics,
488/30895 3/11/2010 4912 4912
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