A previous article, Continuum (Analog) Analysis of Power Integrity, discussed in some detail power integrity (PI), its significance to low-power/ energy design, and the analog technique for simulating PI. This article continues to discuss the significance of PI to floor planning for SOCs and 3D SiPs.

PI-aware floorplanning

A question posed by a customer five years ago was one I had not had the opportunity of analyzing in my experience to that point. It was simple enough; "With voltage regulators providing power to the I/O ring and the core power grid, would it help to connect corner capacitor arrays of the I/O ring into the core grid?" At that point, I was engaged in IR-drop simulations on the chip, a custom clock buffer, analyzing potential issues with power integrity, since supply noise would translate directly into clock jitter that would degrade the output clock signal from the chip. Traditional wisdom and simple IR-drop analyses indicated that additional capacitance would be beneficial in minimizing noise, but I wasn't convinced. We were developing pi-fp, a true-physical, dynamic power-integrity analyzer and chip optimizer, at that point in time, and I jumped at the chance to apply it to the customer's problem.

Figure 1. Simulated snapshot of power grid noise (mv, differential) in a clock chip [right] with and [left] without corner capacitor arrays from the I/O ring connecting to the core power grid. The software used is PI-aware floor planning designer pi-fp. Source: "Power Integrity Analysis and Management for Integrated Circuits," by Raj Nair and Donald Bennett, Anasim Corp., May 17, 2010, Prentice Hall.

The results were, to say the least, revealing and educative! The additional capacitance of ~800pF connecting into the corners of the core power grid reduced peak noise over the core grid area, as seen in Figure 1, from 130mv to 120mv. At the same time, noise propagation characteristics of the distribution grid changed enough that noise increased in regions of the grid that were previously lower noise, where we had instantiated clock buffers in the physical design. Since the clock buffer positions could not be changed in the custom-designed clock tree for this chip, the I/O corner capacitor arrays were not connected to the core grid in this chip design.

Armed with the insight provided by this true-physical simulation capability, I proceeded to analyze other indeterminate aspects of the chip physical design. Investigating the power grid design, it was easy enough to determine the smallest width for VDD/VSS wires that optimized the vector sum of IR drop with LdI/dT noise in the presence of on-die de-coupling capacitance. In fact, I could also determine the least amount of on-die de-coupling capacitance necessary that met the chip's overall PI specifications. Such resource use optimization relaxed constraints on other aspects of the physical design, such as routing, timing, and area available, at the front-end of the physical design flow.

System-in-package considerations

Advanced designs, particularly high-performance ULSI chips, may include components mitigating chip-level PI issues in the package, as shown in Figure 2.

Figure 2. System-in-package component impact on PI in a chip. An Active Noise Regulator (ANR) is seen to minimize dynamic droop (transient reduction in supply voltage on-chip) by 40% in a true-physical simulation. Dynamic droop at locations within the chip with and without an ANR positioned correspondingly opposite in the chip package, with identical dI/dT events, is plotted in the animated image. Software: PI-aware floor planning designer pi-fp, and GNUPLOT.

In the simulated example of an Active Noise Regulator shown in Figure 2, benefits of amplified charge storage and delivery through the use of a combination of silicon circuits and a capacitor result in a PI improvement, a reduction in dynamic voltage droop, of about 40%. High-bandwidth passives such as low-loop-inductance inter-digitated capacitors (IDC's) are commonly employed in microprocessors packages to assist on-chip power integrity. Simulating the effect of devices such as IDC's and ANR's requires spatio-temporal awareness and distributed (true-physical) characteristics in the models employed for valid results. Lumped and RC models are often inadequate to the task of determining true-electromagnetic system behavior. High levels of abstraction and physics-based simulations are, on the other hand, best applied to such advanced analysis requirements, which in turn are driven by low-energy design needs.

Thermal considerations and PI

It's well known that the most active areas of a chip are also the locations generating the most heat, and consequently the hottest regions of the chip. In synchronous CMOS designs, a need to contain power consumption often requires advanced circuit techniques such as clock gating and power gating in these "hot spots." High power consumption and gating techniques often result in high current and dI/dT events in these regions, leading to PI issues. PI issues are hence well-correlated with thermal issues on a chip. PI analysis, therefore, can provide an early view of potential thermal concerns in chip-package co-design. PI mitigation techniques such as the use of greater metal and interconnect resources such as vias (especially with the use of copper) also mitigate thermal concerns through greater heat conduction out of the chip. Minimization of supply oscillations also minimizes energy loss and heat build-up in power interconnect pathways.

3D-integration considerations

As discussed in the source material for this article, electronic integration is headed into the third dimension both at a device level (transistors) and at the package level through stacked packages, chips, and, eventually, to monolithic, 3D fabrication of multiple active and passive components and layers. 3D assembly of chips and packages compound PI and thermal issues due to the greater density of power consuming circuits. More significantly, 3D integration leads to close interactions between stacked chips or systems that were otherwise electrically and thermally distant from each other, as on a printed circuit board, for example.

This leads to additional system-design complexity, where chip floorplanning must include effects from other chips in the stacked array. This requires an ability to capture essential aspects of each chip into a simulation environment, or, in other words, high-levels of abstraction of certain electrical and physical aspects of each chip. An example of such abstraction of a two-stack chip with power input pathways is illustrated in Figure 3. As shown, components of the 3D stack are captured in the form of schematic elements associated with electrical properties as well as spatial (x, y location) characteristics. Temporal aspects of the stimulus (charge demand variation with time) are also captured in the form of distributed current sources associated with functional blocks within each chip in the stack.

Figure 3. A schematic diagram of a two-chip stack, with vias between the two chips offset from each other, and vias to power pathways connecting to an external source. Software: pi-fp.

A 3D view of the schematic is shown in Figure 4. Note that this is a schematic diagram of the planned physical design and assembly of the 3D stack, and does not represent the actual physical design which may be captured in traditional CAD tools. The intent in the schematic capture and integrity analysis of the stacked array is to assist in early, front-end optimization of the floorplan and resource usage in the chip components of the stack, and to detect/ mitigate potential PI and related thermal issues.

Figure 4. 3D view of the 3D chip stack schematic.

A single current source is employed as excitation in the simple experiment shown in Figure 3. This current source block can be seen as the small square between four vias (circles with cross-hairs) on the upper chip in the stack. Simulation results in Figures 5 and 6 show supply noise development on the two chip grids in the stack.

Figure 5. Noise snapshot on the upper chip in the stack at 0.5ns

Figure 6. Noise snapshot on the lower chip in the stack at 0.85ns. Noise is conveyed from the upper chip to the lower chip through the interconnecting vias in this experiment.

Summary

Early PI-aware design is a significant aspect of IC floorplanning, particularly in nanoscale systems where low power/ energy and efficient use of on-chip metal and de-coupling resources are key design constraints. The advent of 3D integration in the form of chip or package stacking makes early front-end analysis of PI through high levels of abstraction and physics-based simulations all the more necessary. Correlation between PI and thermal issues provides an added benefit in front-end PI analysis and optimization.

By Raj Nair.

Raj Nair is the founder of Anasim Corp. and co-author of a recent book on power integrity analysis and management for integrated circuits. This article was based on excerpts from that book: "Power Integrity Analysis and Management for Integrated Circuits," by Raj Nair and Donald Bennett, published May 7, 2010 by Prentice Hall.