The 2009 Semiconductor Technology Roadmap  describes the problems facing future generations of silicon technology. The report analyzes the electrical and manufacturing characteristics for processes and the problems that can affect the success of advanced node implementations. Shrinking device sizes, finer line widths, and longer interconnect make it possible for IC designers to pack more functionality onto a chip, but also reveal a whole new set of design-closure problems.
As physical features and ICs shrink, lithographic and field effects expand, resulting in more numerous and often subtle design-for-manufacturing (DFM) issues. Simple linear spacing, length and width measurements between adjacent features are no longer sufficient. IC design rules now must take into account many three-dimensional geometric measurements related by complex functions to determine if a design is manufacturable at leading-edge process nodes.
Consequently, at 45nm and below, design rules are exploding in number and complexity, making design rule checking (DRC) harder and lengthier. What we see across the industry is that the number of physical verification checks is growing at >20%, node over node — driven primarily by the increase in manufacturing process complexity. What's even scarier is that the number of individual operations required to execute each check is also growing. The total number of operations within a physical verification deck is growing at >30%, node over node.
As a result, IC implementation and verification are becoming much more difficult for IC design and process engineers with limited time and head count. It also creates headaches for IC executives, who need to get advanced products to market quickly with high yield to stay competitive.
With many layout issues coming from both multi-dimensional interactions and combinations of measurements related by complex functions, detection of problematic features is just that, problematic. Using only words, try describing even the simplest structure, like a three-dimensional box. Did anyone understand you? Now draw a simple picture. Instant recognition! Pattern matching replaces the most complex checks that are difficult or impossible to implement in text-based rule-programming scripts with a library of visual shapes and patterns representing geometric configurations in a design.
With this visual representation capability, pattern matching not only provides a whole new way to define, manage, and process design rules, it also allows designers and foundry personnel to communicate easily using a "language" they both understand — pictures.
By eliminating the abstraction and derivation required to develop text-based design rules, and using a visual representation of the configuration, we drastically simplify the process of defining and transferring problem configuration information. Using visual geometries eliminates the use of a syntax that is an abstraction of the original configuration, and uses a format everyone readily understands. But the simplification we can achieve with pattern matching doesn't just reduce the size and complexity of the rule deck, it also increases the accuracy and precision of the DRC process.
So how does it work? We identify problematic topological configurations through manufacturing process simulation, failure analysis, or other verification processes. Once a systematic issue that is related to a particular design feature or configuration is identified and characterized, we can capture it using an interactive GUI, then edit it as needed to define precise measurements and/or tolerances for pattern elements.To complete the pattern definition, we add the pattern specification to a pattern library. Patterns are then "translated" into a format that the pattern-matching engine understands for use in the design comparison.
Naturally, one of the primary beneficiaries of pattern-matching technology will be the people who write design rules. Pattern matching enables design rule engineers to more easily define and manage the complex DRC checks that are critical for designs at 32nm and below. It's much easier to capture a "picture" of a failing configuration than to describe it in words. Likewise, adjusting a picture is much simpler than adjusting a detailed set of design rules. Configurations that prove to fail often in manufacturing or that produce unacceptable performance variations can easily be incorporated into the pattern matching library and passed on to design teams to ensure they are recognized and removed from future designs.
Using automated pattern matching to identify these difficult-to-code geometric patterns lets designers more easily avoid or modify these patterns in the early stages of design implementation and verification, before changes in the layout become difficult and time-consuming.
Conversely, we can use pattern matching to let designers know which patterns can be used. For example, a design team might use static RAM cells in digital ICs that violate the design rule for whatever logic the team has to follow, but which have been carefully designed (and proven) to be manufacturable. Including this pattern in the pattern library assures the design team that they can include this feature in their design without worrying about foundry or yield issues.
Pattern matching isn't intended to be a complete replacement for existing DRC rule decks and process flows. We see it as an extension for rule checks with the highest level of complexity. Users will need to integrate this new capability into their existing physical verification flows in a gradual way as pattern libraries are built up. However, pattern matching does offer the promise of slowing the DRC explosion by providing a much simpler method of implementing the most complex checks found in advanced IC processes.
By Michael White
Michael White is the Senior Product Marketing Manager for Mentor Graphics' Calibre Physical Verification products. He has held various product marketing, strategic marketing and program management roles at Applied Materials, Etec Systems and the Lockheed Skunk Works. Michael received a BS in System Engineering from Harvey Mudd College. He also holds a MBA/BS in Engineering Management from the University of Southern California.
1. The International Technology Roadmap for Semiconductors, http://public.itrs.net/about.html
Go to the Mentor Graphics Corp. website to learn more.