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 Category: SOCcentral Feature Articles & Columns: Feature Articles: Thursday, October 27, 2016
The Need for a Comprehensive SOC Test Platform  
Contributor: Mentor Graphics Corp.
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January 17, 2011 -- Silicon test is the final arbiter that determines if an integrated circuit should be packaged and ultimately shipped to a customer or is defective and should be scrapped. Consequently, a poor test strategy and methodology can have a significant impact on the success of your product. If the test doesn't cover all possible design structures or doesn't provide high enough test coverage, then you could be unwittingly shipping bad devices (that pass the test) to your customers. If you have more tests than needed, or your test is overly constrained, your test cost could be unnecessarily eating into your profit margin. With their diverse structures and almost unfathomable complexity, a modern day system-on-chip (SOC) amplifies the challenge of developing an effective test. The need for a comprehensive test platform to address and manage these challenges has never been so tantamount to business success.

Today's SOC designs are inherently large and complex. In some cases, these designs house 100's of millions of logic gates, dozens of embedded cores from multiple sources, 1000's of discrete embedded memories (many with built-in on-chip repair), analog and mixed signal content, and 100's of high-speed serial I/O. The complexity and diversity in these chips highlight and heighten a fundamental problem that has existed for some time test methods and tools for different parts of the SOC are varied, disjoint, uncoordinated, and difficult to integrate into a comprehensive and cohesive test methodology. This is perhaps not surprising in a technology area characterized by a mix of commercial and one-of-a-kind, home-grown test tools. Typically, these tools don't communicate well with each other, if they communicate at all. As a result, design and test engineers are forced to duplicate, translate and version manage the information flowing between tools, which is slow, inefficient, and error prone. Given this environment, IC test engineers have been forced to become tool developers and solution integrators, diverting valuable resources from their primary mission to ensure the best possible test strategy for their IC products.

If the current state-of-the-practice is less that ideal, what improvements are needed and what can we look forward to? To meet the test challenges of increasingly complex SOCs, the industry needs more comprehensive, commercial test solutions that take a more holistic view of the design and its test needs. An effective SOC test platform is one that allows the designer and test engineer to efficiently plan and implement all the disparate test methods needed to adequately cover all of the components within the device.

This test platform would allow for advanced planning of test strategies for each portion of the design, and assist the test engineer by communicating pertinent information to other tools in the flow. For example, advanced memory BIST planning features can leverage RTL netlists and floorplanning information to determine optimal BIST controller sharing and placement. Memory BIST configuration information can be automatically passed on to automatic test pattern generation (ATPG) so the ATPG tool understands this circuitry and ensures optimal test coverage of all the logic surrounding the memory. Similarly, logic blocks can be analyzed and partitioned during RTL design to determine optimal scan chain and compression configurations, and this information can be automatically passed downstream to ATPG. Likewise, boundary scan implementation can also be done at RTL with downstream integration to ATPG and final netlist verification. In addition, the test platform should embrace and support the unique test demands of analog and mixed-signal circuitry.

By having a complete test development and implementation flow that is capable of sharing information across an interoperable suite of tools, test engineers can be freed from the mind-numbing task of patching together a disjoint set of tests from a disjoint set of tools. A platform that combines all the test technologies needed for an SOC scan, ATPG, compression, logic BIST, memory BIST, boundary scan, and mixed-signal test into a single flow, can allow the test engineer to spend more time planning and optimizing the overall test strategy, and less time worrying about the implementation and tool details. The resulting test set pays dividends in terms of quality, efficiency, and certainly project economics.

Figure 1. Constructing a comprehensive SOC test platform.

But creating a high-quality efficient test set is not the final goal, and a comprehensive test platform doesn't stop at tape-out or after the manufacturing test has been created. A comprehensive platform must also address the back-end challenges related to test those challenges that start after the silicon is tested. Once a test program is applied to silicon, a whole new set of challenges surface, including silicon debug and characterization, failure analysis and diagnosis, and yield analysis and learning. While formerly beyond the scope of manufacturing test, a modern day comprehensive SOC test platform can begin to address this whole new domain of issues.

Having tools that understand the design from a test perspective can provide significant benefits when debugging silicon failures and yield related issues. Test failure diagnosis tools that accurately diagnose the root cause of test failures can dramatically improve failure analysis. As part of an overall test platform, volume test-ailure information can be continuously gathered and diagnosed from production test. New statistical-analysis techniques leveraging the diagnosis data can then be brought to bear on the problem of differentiating random and systematic defects, and zeroing in on the probable cause, impact, and location of systematic defects that would otherwise remain hidden in the noise of random defects. This technique can accelerate yield learning and speed a product's ramp to volume and profitability. Ultimately, information gleaned from this diagnosis-driven yield analysis process can be used to guide the prioritization of recommended design rules and to calibrate design-for-manufacturing (DFM) processes and scoring methods.

If it seems like the potential for improving the test process is almost limitless, that's because it is. We are now entering a long-overdue renaissance in SOC test, driven partly by necessity, and partly by innovation. The vision of this new era involves orders-of-magnitude improvements in tools with streamlined communication processes to allow hard-working test engineers to refocus on the task at hand. With improved tools and an integrated process, developing a high-quality and efficient test set for the entire chip becomes a more predictable and achievable process, significantly reducing the cost of test. When an effective test set is applied to silicon, useful data can be mined and intelligently fed back to the design process to accelerate yield improvements. Overall, an integrated approach to test can deliver dramatically improved test quality, time-to-market and project economics.

By Greg Aldrich.

Greg Aldrich is the Director of Marketing for the Silicon Test Solutions product group at Mentor Graphics. In the last several years, Aldrich has held a variety of technical and product marketing positions at Mentor Graphics, most recently as a product marketing manager within the design for test (DFT) group. Prior to joining Mentor, Aldrich served as an applications engineer at Sunrise Test Systems and, previous to his work with Sunrise, spent 10 years as a systems design engineer and engineering manager at Amdahl Corp.

Go to the Mentor Graphics Corp. website to learn more.

Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, design for manufacturing, design-for-manufacturing, DFM, BIST, built-in self-test, automatic test pattern generation, ATPG, SOCcentral, Mentor Graphics,
488/32945 1/16/2011 3950 3950
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