June 2, 2011 -- Implementing an FPGA design used to be straightforward. It was almost as simple as pressing the big RUN button on your synthesis tool followed by automated place and route. Out popped an initial incarnation of your design. You could create the entire design "top-down" and observe the results on the board in a matter of a few hours. Design setup was easy too: it consisted of a single design project whose timing objectives you specified at the top level, leaving the nuts and bolts of creating the best implementation to the tools. Synthesis tools were measured by the quality of their push-button timing and area results. This was a win-win for the tool and designer because this "top-down, make it all happen under the hood" strategy afforded maximal timing and area optimization opportunities, leading to the best possible results for the design.
While top down implementation methodologies still work well in some cases, there are a number of situations where a hierarchical design methodology may be more appropriate. These include:
- Designs requiring timing or results stability. Such designs may contain significant pre-verified IP modules that you want to preserve; or the designs, nearing completion, have met design goals for the most part and require final targeted improvements.
- Designs where there is a need to "divide and conquer," that is to say the need to make independent progress by carving out pieces of a design for autonomous additional development and test. For example, your design may have some modules that are ready for verification and others that have not even been started. You may have one module that you need to isolate because it is not meeting its targets and needs focused debug. You may need to define specific clear-cut boundaries in the design that you can preserve and monitor. You may have team members that are accelerating progress by developing partitions of the design in parallel. You may want to reuse specific IP that already works with your current system software.
Figure 1. Designs typically include portions that are being reused along with third-party IP; they may be divided into portions that are timing critical and portions that are not; and each portion may be at a different stage of development or not yet available at all.
Today's FPGAs implement the equivalent of millions of ASIC gates. At this scale, iteration run-times for the FPGA from RTL to board, can consume an entire day. This is where hierarchical design comes to the rescue by allowing you to isolate and address those parts of the design that are in need of immediate improvement or are not functioning correctly. For example, you can iterate and refine one very high-performance path and concurrently isolate another module that is failing for some reason and is ready for debug. Slot in your pre-designed embedded processor or datapath implementation of choice as a subsystem of the overall design.
Dealing with hierarchical design challenges
Design processes are migrating from the top-down methodology to a more "bottom-up" create-and-merge approach. While this hierarchical approach to design offers a lot of flexibility, it also introduces some challenges, such as meeting timing constraints, managing FPGA resources, implementing a mechanism to automate the isolation of circuitry and creating and integrating sub-modules, not to mention keeping the design effort synchronized.
Meeting timing requirements
The trade-off with hierarchical design can be performance optimization, unless you deploy specific techniques. In so-called bottom-up hierarchical flows where modules are merged at the netlist level, cross-boundary optimizations may be limited and can limit overall performance. It is, therefore, critical in any hierarchical design flow that you:
- Implement time budgets so that the tools know what targets they must meet; highly automated time-budgeting features or interface timing information within the synthesis tools can more easily allow timing goals of individual and surrounding modules to be met such that each block can now be optimized in the context of its surroundings.
- Register your I/O boundaries.
- Plan up front to isolate critical paths inside a given hierarchical module to maximize timing-optimization possibilities by the tools.
Sub-module isolation for debug
Tools now need to provide automated ways to partition and isolate timing-critical or high-reliability parts of the design so that these portions of the design can be iterated quickly and more easily analyzed and debugged. The tools must later allow sub-modules to be merged back together bottom-up style at the netlist level, once a working netlist for each sub-module has been created.
FPGAs can present some different challenges from ASICs to achieving hierarchical implementation. This is particularly true in the area of FPGA resource management. The FPGA has fixed resources such as memory blocks, arithmetic blocks, clock resources and embedded hard IP. Some design teams may be able to floorplan blocks and allocate resources at the beginning of the design phase. But in many cases, resource allocation is not completed or even considered until the implementation phase. Floorplanning, while helpful, should not be a requirement. Design tools should take care of managing FPGA resources automatically.
Distributed design — the need for synchronization
If the design's development is to be distributed in a "team design" approach, it's critical to have design file version control and design block export features for ease of implementation of modules in parallel, followed by the merging back together of individual design components for final implementation.
Whereas in the past a single engineer might have specified, implemented and verified the design, the function may now be split across separate teams with, for example, design RTL hand-off occurring nightly to the verification and system software development teams.
The separate groups of hardware, software and verification engineers need the ability to independently make progress on different modules, yet stay synchronized.
Similarly, the engineers in a team performing FPGA-based prototyping of their ASIC might receive updates to the RTL for specific ASIC modules nightly and need to run with that snapshot as they proceed to verify its operation.
Figure 2. Nightly snapshots of the evolving hardware to be handed off to the verification and software teams so that they can make progress.
Today's FPGAs may contain the equivalent of millions of logic gates and hundreds of thousands of lines of embedded software. Such designs may involve multiple hardware design teams, software development teams and verification teams located around the globe. The newest generation of FPGA design tools need to respond by supporting hierarchical design approaches. The use of IP abounds, as does the need to make independent progress on focused portions of very complex designs — the ability to mix and match and swap different versions of a sub-module into and out of the design is critical. Specific tool features such as block-based incremental and hierarchical design allow you to achieve timing and design stability while isolating those portions of the design in need of improvement. Resource and timing budgeting are vital so that you can develop each part of the design autonomously yet in the context of the rest of the design.
With the design-development function becoming increasingly distributed across multiple design and verification engineers, machines and time-zones, parallel development of designs is the wave of the future. Clear synchronization and hand-off using version control is a must in order to have coordinated development of the design.
The ability to use hierarchical team-based design is now seen as being mission-critical by any company involved in the creation of one of today's high-end FPGA designs, making true hierarchical team-based design one of the most requested features of FPGA tool providers.
By Angela Sutton.
Angela Sutton brings over 20 years of experience in the field of semiconductor and semiconductor design tools to her role as Staff Product Marketing Manager for Synopsys, Inc. In this role, she is responsible for the FPGA Implementation product line.
Prior to joining Synopsys, she worked as senior product marketing manager in charge of FPGA Implementation tools at Synplicity, Inc., which was acquired by Synopsys in May 2008. Ms. Sutton has also held various business development, marketing and engineering positions at Cadence, Mentor Graphics, Responsys, and LSI Logic. At LSI Logic she was responsible for marketing LSI Logic's line of digital video semiconductor products and platforms.
Ms. Sutton holds a BSc. in Applied Physics from Durham University UK, and a Ph.D. in Engineering from Aberdeen University UK.
Go to the Synopsys, Inc. website to learn more.