September 20, 2011 -- Delay testing is widely used to check whether a manufactured chip is free of delay defects and meets its performance specification. Common delay testing methods such as logic BIST and at-speed scan testing are applied to industrial designs with good results. But as process nodes shrink, delay defects take on more subtle forms involving once secondary effects such as interconnect, cross talk, process variations, and power-supply noise.
Timing-aware ATPG and logic BIST tools are addressing the need to use more sophisticated delay fault models and robust test constraints; engineers are burdened, however, with significantly longer run-times and more complex mitigation steps to raise test coverage to acceptable levels compared to previous practices. This article will review at-speed testing approaches and introduce new automatic methods of analyzing and improving at-speed scan-based design for testability through early RTL analysis and design.
Brief overview of at-speed test
There are three main methods for at-speed testing:
- At-speed scan test.
- Faster-than-rated clock scan test.
- Logic BIST.
These approaches support a variety of delay fault models accurate enough to test for delay defects. Our focus is on at-speed scan-based testing.
Types of test cycles
At-speed scan testing utilizes one of several scan test cycle approaches:
Launch on Shift (LOS) - In LOS, the transition is launched in the last shift cycle during the scan-shift operation. This activates the required transition at the target node or path which is then propagated and captured through the functional path at the observable point (Din) of any flip-flop our primary output port of the chip. In recent years, leading industry players have developed a more advanced LOS method, called Burst Mode, that better allows the design power supply and clocks to stabilize before the launch and capture cycles (see Figure 1A.) The scan chain is loaded as normal except that it is extended by 3 flops. When the clock source is switched over from the slow scan clock to at-speed functional clock, the scan chain remains in shift mode until the final two clocks in Burst Mode, which is when launch and capture is performed.
Launch off Capture (LOC) - In LOC, the transition is launched and captured through the function pin (Din) of any flop-flop in the scan chain (see Figure 1B.) Since the launch pattern depends on the functional response of the loaded scan pattern, the launch path is less controllable and test coverage may be more difficult to achieve. Because LOS puts more difficult timing constraints on the Scan Enable signal, LOC is more widely deployed and runs on low-cost testers.
Figure 1A. Launch on Shift (LOS) Burst Mode test cycle timing diagram.
Figure 1B. Launch off Capture (LOC) test cycle timing diagram.
The quality of a set of tests can be classified by the concept of robustness. A test is called robust if, and only if, it detects the fault independent of other delay faults in the circuit. Non-robust tests guarantee the detection of a fault if there are no other delay faults in the circuit. If there is neither a non-robust nor a robust test, the delay fault is untestable. Robust and non-robust tests differ in the constraints on the off-path inputs of the path; notably they both must be non-controlling. In robust test, however, they have to be stable values throughout the test cycle. In Figure 2, the on-path transition is launched at q3 while the off-path values of q1 and q2 must be 0 throughout the test cycle. In ATPG, robust test refers to the robust fill method, while non-robust test mode refers to the random fill method.
Figure 2. Path delay fault launch->capture path (q3->w4).
At-speed delay fault models
There are several delay fault models used in at-speed ATPG and Logic BIST
- Path-delay fault (PDF)
- Transition-delay fault (TDF)
- Small delay defect-transition delay fault (SDD-TDF)
Path-delay faults (PDF) model distributed delay defects. When the cumulative delay along a targeted path exceeds the clock cycle and setup time, a path delay fault occurs. The effect of the delay may be different for a rising or falling transition so two PDFs (rising and falling transitions) are required for each physical path.
Transition-delay faults (TDF) model a spot delay defect on a single node that is assumed to be large enough to exceed the timing slack along any propagation path to the output or flip flop. Thus, gross local faults and faults distributed across a large area are covered by this fault model. Due to differences in slow-to-rise and slow-to-fall timing, 2 transitions are necessary per node. Assuming m signals in the circuit, 2m transition-delay faults (TDFs) can be modeled.
Small delay defect-transition delay faults (SDD-TDF) model the small delay variations induced by cross talk, process variations, power-supply noise, as well as resistive opens and shorts, can potentially cause timing failures in a design, thereby leading to quality and reliability concerns. A SDD is a defect with defect size not large enough to cause a timing failure on its own. An SDD might escape during test application when a short path is sensitized since the accumulated delay of the distributed delay defect is not large enough to cause a timing violation. In contrast, the same SDD might be detected if a long path is sensitized. In Figure 3 the SDD-TDF at w4 should be tested along the path from q3->w2->w3->w4 since the measured slack time is the least. Unfortunately, common ATPG algorithms usually prefer short paths since the sensitization of these paths is typically easier.
Figure 3. Transition-delay fault long path and short paths.
Figure 4. Critical timing path waveform.
Timing-aware ATPG is needed for PDF and SDD-TDF testing including the robust test method. Here, pre-calculated timing slack information is used during structural ATPG to guarantee sensitization of the longest path and will be more likely to detect SDDs. Timing-aware ATPG is a computationally intensive task, however, Because the search space is very large. As a result, the run-time of timing-aware ATPG increases significantly compared to regular ATPG and coverage results will not be nearly as high as with simple stuck at or TDF models.
RT-level DFT overview
Given the generally lower coverage results with PDF and SDD-TDF, significantly longer ATPG runtimes, and more complex design changes required to improve coverage, it is imperative to consider new approaches for at-speed DFT. One such approach is to start working on design for testability issues earlier at the RT-level.
Specifically RT-Level at-speed DFT testability analysis and repair can lead to higher ATPG test coverage in less time. The Avery Design Systems' Insight DFT solution, as shown in Figure 5, is one such early RTL DFT solution comprising:
- Automatic DFT testbench generation.
- DFT design rule checks.
- Robustness checks.
- PDF testability coverage.
- Automatic RTL repair.
Figure 5. RT-level at-speed DFT flow.
Scan design intent
Performing accurate testability analysis on RTL requires knowledge of how the design will operate in at-speed test mode. Common information necessary to express the full scan design intent includes defining scannable and non-scannable registers, X-generators, test mode clock schemes, I/O pin modes, memory bypass modes, external clock sources and test pins, false and multi-cycle paths, and LOS, Burst Mode, or LOC test cycle operation. The following is a typical Insight DFT setup script.
DFT design rule checks
Using Insight DFT, initial screening of the design for DFT rules can find obvious testability issues associated with operating in test mode. Repairing the design for these situations will improve overall test coverage. These checks focus on finding and identifying mixed clock and data signals and X generators. Further X propagation analysis can be used to determine whether the X’s propagate or whether they are blocks in test mode.
At-speed PDF testability analysis
Next, Insight DT can make an initial SDD-TDF and PDF test coverage estimation based on targeting the high-fanout critical paths in the design. Assessing what paths are most critical in the RTL is based on combinational logic complexity heuristics. Because the PDF model generates an exponentially large number of register-to-register paths to analyze, Insight uses a sampling approach of the highest-fanout paths to analyze for at-speed testability. Insight will generate a PDF summary report that identifies which paths are detected robustly along with the number of paths that are not detected for any number of testability issues, for example:
- X generator XG 0
- Non-scannable register UC 0
- Unobservable capture register OB 0
- Cross clock domain unblocked CD 0
- Launch register non-scannable NS 0
- False path FP 0
- Multicycle path unblocked MP 0
In addition, a detailed untestable path report ranked by combinational logic complexity is also generated for detailed investigation. Here the rising and falling launch conditions are reported separately.
At-speed robustness checks
When using LOC, SDD-TDF and PDF requires using the robust fill ATPG test-generation algorithm to ensure these delay fault types can be detected independently of other delay faults in the circuit. This mode of ATPG is very time-consuming because of the additional constraints compared to random-fill ATPG. Early RT-Level DFT analysis is able to identify the most interesting circuit paths in the design and analyze them for robustness, specifically that certain flops in the logic cone of the path under test can remain stable throughout the at-speed test cycle. If the design's logic cannot be controlled deterministically in test mode, then ATPG test coverage will suffer. The analysis performed using Insight DFT will identify the high-fanout paths in the design and analyze them for adherence to robustness constraints. Once identified, these paths can be repaired and result in higher SDD-TDF and PDF test coverage.
Automatic RTL repair
Fixing testability issues in the RTL is tedious and error prone. Automatically generating RTL repairs is an important step that will result in higher testability based on test-overhead constraints set by the designer. The top at-speed robustness checks can be targeted for repair and evaluated for the estimated number of paths fixed and additional logic overhead. In LOC mode, design repairs can fix controllability and robustness issues by inserting controllability points in the design automatically. These repairs can be optimized for the test logic overhead by reusing existing scannable flops to add the new logic paths to ensure improved controllability. The designer can evaluate if the test overhead is too high and then alter the repair list until it is within acceptable bounds.
Post repair at-speed PDF testability analysis
After RTL repairs are made, Insight DFT performs another SDD-TDF and PDF test coverage estimation run based on targeting the same high-fanout critical paths in the design as the initial run. This run confirms the increased number of paths that are detected robustly as a result of the repairs.
After the RT-level DFT analysis and repairs have been completed, the design is ready to go through logic and test synthesis and ATPG. By performing repairs at the RT-Level, all the changes can be optimized by logic synthesis tools for timing closure.
Timing-aware ATPG is necessary to address the need to use more sophisticated delay fault models such as SDD-TDF and PDF. But this results in significantly longer run-times and more complex mitigation steps are necessary to raise test coverage to acceptable levels compared to previous practices. Early RT-level testability analysis and repair can analyze and diagnose test issues dealing with robust test generation and yield better first-pass ATPG results.
By Chris Browy
and Kai-hui Chang
Chris Browy is co-founder and Vice President of Sales and Marketing of Avery Design Systems, Inc. Chris has 27 years of experience in the fields of IC design, professional design services, and marketing front-end EDA tools. He is a graduate of Rensselaer Polytechnic Institute.
Kai-hui Chang is an architect working on Avery Design Systems, Inc.'s formal product called Insight. Kai-hui received his Ph. D. from University of Michigan at Ann Arbor and is the recipient of ACM's Outstanding Dissertation Award in EDA at DAC'09. He has 11 years of experience in EDA and has published more than 20 papers in this field.
Go to the Avery Design Systems, Inc. website to learn more.