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 Category: SOCcentral Feature Articles & Columns: Feature Articles: Friday, September 19, 2014
A Verification Methodology for 3D-ICs  
Contributor: Mentor Graphics Corp.
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October 3, 2011 -- The use of three-dimensional integrated circuit (3D-IC) techniques has been growing in importance because 3D provides a way to increase both data throughput and the amount of functionality on a chip without using more costly leading-edge technology nodes. By going up instead of out, the connection between any two given points is shorter and has lower parasitic resistance and capacitance values, enabling wider buses and smaller drivers for inter-chip communication. Other advantages of 3D-IC are lower power consumption, the ability to use multiple technologies across different chips (heterogeneous technology integration), and reduction in the form factor of the final product. Because of these advantages, many companies are now turning to 3D-ICs for their next-generation products.

Like any new technology, however, 3D-IC has little value if the accuracy and manufacturability of the chip cannot be verified. New verification techniques are needed to ensure that 3D-ICs meet performance and manufacturing requirements.

What is a 3D-IC?

A 3D-IC is a chip that has multiple layers of active electronic components that are integrated vertically and/or horizontally into a single package. A through-silicon via (TSV) is used to create connections though the silicon, connecting the top metal layers (front metal) to the bottom metal layer (back metal).

Figure 1. The through silicon via (TSV) connects the front metal to the back metal layers.


This differs from a traditional chip in that a traditional chip only contains front metal layers, with no vias going through the silicon.

These chips with TSVs are then stacked on top of each other and connected through microbumps (copper pillars). The stacked chips are attached to the package substrate through flip chip bumps, also known as Controlled Collapse Chip Connection (C4) bumps.

Figure 2. Stacking multiple chips with TSVs together to create a 3D-IC.


There are some technology issues that are still being researched, including TSV formation, die thinning, thinned die handling, assembly, and testing. However, TSMC has recently announced that they are ready to make 3D-IC chips commercially available before the end of 2011:

"With several layers of silicon stacked together, a 3DIC chip can achieve performance gains of about a third while consuming 50 percent less power. For this reason, 3DIC chips are particularly well suited to power new generations of mobile devices such as tablets and mobile phones." Source: "TSMC May Beat Intel With World's First 3D Chips", PCWorld.

Other foundries and integrated device manufacturers have stated their intentions to provide products in the 3D-IC space, and we will begin to see increased commercialization in the coming year.

3D-IC configurations

There are different configurations of 3D-IC: vertical die-to-die stacks (3D stacking), silicon interposer integration (also called horizontal integration, or 2.5D), and various mixed configurations.

The stack configuration shown in Figure 3 represents the initial approach, as proposed by the design houses and the foundries, to constructing efficient 3D-IC systems.

Figure 3. 3D-IC with TSVs connecting front and back metal layers (3D stacking).


In this example, there is a double-sided logic die with TSVs connecting the front metal1 layer and the back metal1 layer, and a standard memory die containing only active circuitry and front metal layers (no TSV or back metal). The two chips are stacked on top of each other, and connected with microbumps. The two connected chips are attached to the package through the use of C4 bumps.

There can be one or two redistribution layers on the back side of a chip, with microbumps connecting the chips. Alternatively, to reduce the cost, TSVs can be directly connected from the front metal1 to the microbumps on the back side. Such chips can then be connected back to front, back to back, or front to front. The configuration shown in Figure 3 results in a so-called "true 3D" design. It also allows for increased performance and a reduction in power requirements.

While the typical approach uses a "via middle" process (i.e., the TSV is formed after FEOL and before BEOL), there are technological challenges to fabricating TSVs with this approach; for example, a shift in the transistor characteristics can be introduced that would significantly and unpredictably affect the system performance. Because these TSVs affect the active devices, the use of interposers for 2.5D stacking was developed as a way to get some of the benefits of stacking, without putting TSVs through chips with active devices.

2.5D stacking uses silicon-based interposers to horizontally connect multiple chips. An interposer is a silicon or glass substrate with metal interconnects used to create electrical routing. Figure 4 illustrates a 2.5D stack connecting three chips with active circuitry (such as logic or memory chips). The chips are flipped upside down, and connected with microbumps to an interposer that has metal routing connecting the different chips. TSVs through the passive interposer connect the front of the interposer to the back of the interposer, allowing those nets to connect to the package substrate through C4 bumps.

Figure 4. 2.5D stack containing three standard chips with active circuitry and top metal, connected through an interposer with TSVs.


One of the earliest production 3D-ICs announced was the Virtex-7 FPGA by Xilinx, which used silicon interposers to create a high-performance FPGA.

"Xilinx today announced the industry's first stacked silicon interconnect technology for delivering breakthrough capacity, bandwidth and power savings using multiple FPGA die in a single package for applications that require high-transistor and logic density, as well as tremendous levels of computational and bandwidth performance. By embracing 3D packaging technologies and through-silicon vias (TSV) for its 28nm 7 series FPGAs, Xilinx's Targeted Design Platforms can address systems with resource requirements that are more than double the reach of the largest single-die FPGAs." Source: Xilinx Press Release.

To reduce potential problems with long interconnection delays, Xilinx partitioned the chips so that each chip only had to communicate with its immediate neighboring chips. In addition to reducing stress, the interposer-based configuration also simplifies the power distribution problem, which can be very significant in true-3D stacking.

Verification methodologies for 3D-ICs

Configurations for the stacks must be properly described for accurate design and verification. The emphasis is on the precise description of the interfaces (chip-to-chip or chip-to-interposer), so that an appropriate and efficient verification process can be developed.

A rule file, used to describe a 3D stack, typically contains a list of dies with their order number, the information for each die's position, rotation, and orientation, as well as the location of the GDS files and associated rule files and svdb directories. The interface type and the rules (both DRC and LVS) are specified in the interface rule files.

For parasitic extraction of the chip interfaces, descriptions of the dimensions and electrical characteristics of the interface materials (microbumps, copper pillars, bonding material properties, etc.) are needed, as well as the number of layers that should be taken into account from the neighboring dies (up and down) for parasitic extraction.

3D-IC stack verification, regardless of the configuration, includes DRC, LVS, parasitic extraction (PEX), and simulation. The approach taken today is to first run DRC/LVS/PEX on the individual dies separately, and then to consider the interfaces. For the interfaces (between the vertically stacked dies, as well as between the dies and an interposer), a separate GDS consisting of the interface layers is formed , and then DRC and connectivity checking are performed against this GDS. Text labels should be inserted at the interface microbump locations to enable the connectivity checking between dies. Based on stack information (die order, x,y position, rotation, orientation, etc.), provided in a rule file, the tools perform DRC and connectivity checking on the entire stack.

At Mentor Graphics, this technique is used today by Calibre 3DSTACK. Parasitic extraction with Calibre xRC or xACT 3D is then used to extract the front metal, as well as the back metal (BRDL layers).

Figure 5. Calibre DRC, LVS, xRC and 3DSTACK used for 3D-IC verification


TSV models and extraction

A TSV can be modeled as an LVS device or as a via. Often, device model subcircuits are provided for a TSV. These models are obtained by S-parameter measurements and circuit parameter extraction. In these flows, the TSV device model would then be connected to the parasitics on both the front and back side. Using a TSV device model is adequate for some applications, such as regular layouts with no redistribution layer (RDL), low-density TSVs, and interposer-based configurations.

One of the problems with isolated TSV device models is that they are not adequate for high-density, high-frequency applications, due to the non-uniform environment around the TSVs. Also, isolated device models do not account for TSV interactions with other TSVs (capacitive or inductive couplings), or to interconnect (TSV to RDL and metal lines).

Alternative modeling approaches being considered are single TSV models, compact models, and a field solver approach. The benefit of a single TSV model is that it is easy to integrate into a flow, and that it is sufficient for most present needs. The challenge is that it is not adequate for high-density, high-frequency applications. The advantages of using a compact model are that some interactions can be taken into account, and that it is faster than a field solver, but the disadvantages are that it is hard to account for all situations, and it is difficult to parameterize for all important variables. The field solver approach has one significant advantage in that it is the most accurate approach, but the challenges are slower performance and integration. Many of these issues are being actively researched by universities, integrated device manufacturers (IDMs), and electronic design automation (EDA) companies.

In summary

The use of 3D-IC techniques provides companies with ways to gain speed advantages and to increase the amount of functionality on a chip, while reducing the form factor and power usage. Verification techniques are already in place to enable designers to verify their 3D-IC designs, while further research in the area of TSV modeling will enable more accurate characterization in the future.

By Karen Chow

and Dusan Petranovic

Karen Chow is a Technical Marketing Engineer in the Design-to-Silicon division of Mentor Graphics Corp. in Wilsonville, Oregon, focusing on driving parasitic extraction development in analog and RF design flows. Prior to joining Mentor Graphics, Karen worked in the telecommunications and EDA industries, designing analog ICs and supporting EDA tool development. She received her Bachelor of Science degree in electrical engineering from the University of Calgary, and her MBA from Marylhurst University. Karen can be reached at karen_chow@mentor.com.

Dusan Petranovic is a Technical Marketing Engineer in the Design-to-Silicon division of Mentor Graphics Corp. in Wilsonville, Oregon. Dusan has extensive experience in the semiconductor industry, publishing numerous papers and holding twelve U.S. patents. He received his B.S. in Electrical Engineering from the University of Belgrade, an M.S. in Computer Engineering from Worcester Polytechnic Institute, and his Ph.D. from the University of Montenegro, where he was employed as an associate professor. Dusan can be reached at dusan_petranovic@mentor.com.

Go to the Mentor Graphics Corp. website to learn more.

Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, 3D ICs, 3D chips, stacked ICs, EDA, EDA tools, electronic design automation, verification, packages, packaging, SOCcentral, Mentor Graphics,
488/34804 10/3/2011 3439 3439
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