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 Category: SOCcentral Feature Articles & Columns: Feature Articles: Wednesday, October 26, 2016
Completing Hardware Innovation Cycles in Less than Six Months: An Internet Data Center Server Case Study  
Contributor: Synopsys, Inc.
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February 1, 2012 -- New market developments and the pressure to leapfrog the competition make it imperative for companies to roll out the next-generation version of their products in record time. Companies that develop ASIC-based systems are rising to the challenge through a variety of means, including deployment of easily reconfigurable modular designs that can be surgically updated to improve them, implementing some functions in software so that all that is needed is a software upgrade, or validating ASIC operation using FPGA-based prototyping boards to uncover issues that only become visible when the system is running at speed.

In a best case scenario, enhancements for the next-generation product are as simple as applying a software upgrade to an existing hardware system to introduce new or improved functionality. Some competitive innovations, however, such as the need to deliver higher throughput, lower power consumption or faster performance, are largely hardware-dependent and necessitate a hardware design re-spin with the assurance that the design will still work. This is where rapid FPGA-based prototyping can help.

Let's consider, for example, the development of the SM10000-64HD server by Silicon Valley-based SeaMicro, Inc. The company differentiates by delivering high-density, low-power servers optimized to handle the most common Internet workloads. Specifically, the SeaMicro SM10000-64HD server is an x86 compatible system that delivers the same performance as competing servers, yet uses just one-quarter the power and occupies one-sixth the space. In just over a year, the company delivered three new server systems, each time improving energy efficiency and compute density.

Figure 1. Each SeaMicro server component is engineered to have an extremely small form factor. Each server is networked together via the ASIC to create a supercomputing cluster that uses just one-quarter the power and one-sixth the space of conventional servers. Multiple servers per PCB motherboard are stacked to create the SeaMicro SM10000-64HD server, which replaces 60 traditional servers.

SeaMicro was able to achieve this by:
  • Rethinking the entire server architecture, bearing Internet workload in mind
  • Using FPGA-based prototyping to validate and improve the design at speed

Let's talk a little about the second item, i.e., FPGA-based prototyping.

Validating and improving the quality of the design

SeaMicro used Synopsys' Synplify Pro software to synthesize the ASIC in an FPGA and to validate the operation of the ASIC design using a Xilinx Virtex 5 FPGA-based prototype of the ASIC design. This approach allowed SeaMicro not only to validate the design "at speed" but also to significantly improve the design coverage, optimize overall development costs and, most importantly, get the product into the hands of customers.

FPGA-specific implementation tools are key

SeaMicro sought to validate as much of its ASIC as possible in a single FPGA device so that it could maximize test coverage and reduce risk. During the course of generating the prototype, it was important to fit the maximum amount of the ASIC into a single FPGA and it was critical that the synthesis tool met timing-performance goals for the design. FPGA-specific timing and area optimizations played a role in optimizing the design prototype such that SeaMicro was able to re-use the same hardware prototyping board across multiple generations of its server product.
  • Smaller FPGA area during synthesis translated to higher ASIC test coverage.
  • Smaller, more efficient implementations of an ASIC prototype translate into the ability to implement and validate more of the ASIC in a single FPGA prototype.

How does one achieve the smallest implementation of the design in an FPGA? To answer this, it's important to know that an FPGA chip architecture is fundamentally different from an ASIC. The FPGA comprises specific building blocks, typically memories, DSP primitives, registers and lookup tables (LUTs). The building block resources chosen when creating the prototype can have an impact on area results and, therefore, determine the size and cost of the FPGA that must be used to implement the design. The FPGA-synthesis tool must understand how to optimize and improve the efficiency of using these FPGA resources.

For example, moderately sized RAMs, ROMS, counters, large adders and shift registers can be implemented in the FPGA's dedicated block RAM in lieu of consuming available logic resources. Very small memories can be implemented in available registers called distributed RAMs. This choice is made automatically during synthesis, but the tool lets users control the choice of resources. The designer can traverse the synthesis design database to locate non-timing-critical paths, shift registers or registers associated with arithmetic elements, and then force more area efficient implementation or "packing" using on-chip resources such as FPGA RAMs, I/O buffers or DSP elements.

All this is fine, but how about a real example of why area optimization matters? SeaMicro's most recent ASIC design project had increased hardware functionality by approximately 15% compared with the prior generation, and the new design was expected to fill the FPGA on the prototyping board used in the previous generation design to well beyond capacity. To avoid the need to re-spin the prototype board itself to incorporate a larger FPGA, which would have incurred project delays, SeaMicro deployed synthesis software with FPGA-specific optimizations to squeeze the additional functionality into the same Virtex-5 FPGA-based prototyping board used for SeaMicro's previous-generation design. This made it possible to validate more of the design to ensure that it operated correctly.

Accurate FPGA timing optimizations ultimately enabled at speed validation

Validating an ASIC's operation "at speed" can reveal many design flaws and is a valuable tool. To implement an FPGA prototype that achieves the desired speed goals requires detailed knowledge of the FPGA architecture, and the ability to accurately predict timing and understand true critical paths. It is important to understand that the FPGAs used in a prototype contain defined clocking and routing architectures that greatly impact timing performance as well as implementation choices. Synthesis tools that understand how to predict the timing of paths in the FPGA and how to improve timing using FPGA resources are crucial if one is to meet timing goals in the prototype. FPGA synthesis tools are critical since they can perform FPGA architecture-specific optimizations targeting the LUT, register, memory and DSP resources on the FPGA. Timing for all building blocks in the FPGA are accurately modeled to help drive optimization of the true critical paths.

In summary

Pressures to deliver next-generation products to market, without compromising quality, are fundamentally changing the way designers create products. Many designers are architecting their products with change and the need for quick upgrades in mind. FPGA-based prototyping of the design is an attractive option that provides quick feedback on the operation of the design. This approach, utilizing FPGA-specific synthesis tools to generate these ASIC prototypes efficiently, and with the required performance, enables companies such as SeaMicro to deliver up to three brand new generations of product per year.

For more information, please visit

By Dhiraj Mallick

and Angela Sutton

Dhiraj Mallick leads the Hardware Engineering group at SeaMicro, Inc.. Dhiraj brings a proven track record of execution and more than 15 years experience in the computer and semiconductor industry. Prior to SeaMicro, he was Vice President of Engineering at MetaRAM, a VC-backed semiconductor startup, where he delivered into production two generations of products in 30 months. Prior to MetaRAM, Dhiraj spent 10 years at Advanced Micro Devices.

Angela Sutton is Staff Product Marketing Manager, FPGA Implementation and brings over 20 years of experience in the field of semiconductor and semiconductor design tools to her role. Prior to joining Synopsys, Ms. Sutton worked as senior product marketing manager in charge of FPGA Implementation tools at Synplicity, Inc., which was acquired by Synopsys in May 2008. Ms. Sutton has also held various business development, marketing and engineering positions at Cadence, Mentor Graphics, Responsys, and LSI Logic.

Go to the Synopsys, Inc. website to learn more.

Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, verification, emulators, emulation, FPGA-based prototyping, Synopsys, SeaMicro,
488/37655 2/1/2012 5907 5907
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