May 11, 2012 -- Transaction Generator (TG) is a freely available, highly-versatile tool SystemC simulation tool for benchmarking network-on-chips (NoCs). TG is developed at Tampere University of Technology, Finland, in collaboration with other members of the OCP-IP Network on Chip Working Group. The TG generates traffic for NoCs according to abstract models for software workload and system-on-chip (SOC) hardware. During simulation it measures performance metrics for the application, platform, and the traffic routed through the NoC.In addition to the clock-cycle-accurate mode, TG can work also at the transaction level, which is substantially faster for simulating large systems. Figure 1. shows the overall concept. TG models the stimulus events from the environment, tasks, processing elements, and generates traffic. The evaluated NoC is a separate model. After the simulation, the statistics can be visualized and inspected using a tool called Execution Monitor that is included with the TG package.
Figure 1. Transaction Generator creates traffic to the benchmarked network-on-chip. Traffic is generated according to an abstract data-flow model that mimics the application's behavior.
Two major updates have been implemented recently: support for dynamic random-access memory (DRAM) models and MCSL benchmarks. The Accurate DRAM Model (ADM) is a configurable, transaction-level model developed at Royal Institute of Technology (KTH), Sweden. It considers the major delay parameters of real DRAMs and imitates their realistic timing behavior by capturing access dependencies, (for example, row and bank activation,) as well as access granularity (burst-length larger than one word). This way it can be used to test the delay and throughput of the memory subsystem for certain traffic flows. The integrated memory model enables two additional modeling features for TG: cache misses and shared-memory communication.
Earlier versions of the TG supported only message passing and assumed that programs fit in the local instruction memories of the Processing Elements (PEs). Now, a PE will be stalled upon cache miss until it has been served by the main memory. Moreover, the tasks can read their input data from a memory or store the results to it, in addition to direct PE-to-PE communication. Few changes to the input XML format (and lots of changes to the code!) were made to incorporate these new features.
The TG package has already included a basic set of 9 traffic models from the multimedia and telecommunication domain and now it can also execute benchmarks developed at Mobile Computing System Lab (MCSL ) of Hong Kong University of Science and Technology. Detailed communication traces have been recorded from cycle-accurate system-simulation using realistic applications, such as H.263 encoder, H.264 decoder, robot control, and satellite receiver. Moreover, MCSL set also includes abstract, statistical versions which help to accelerate NoC explorations. The utilized model is a task communication graph which is very similar to TG's native format and, hence, the integration went smoothly. Users can select the model-type with command-line parameters and the TG completes the conversion automatically.
The whole TG toolset is feely available to both OCP-IP members and nonmembers. System-level designers can use it for evaluating various design choices of a complex system-on-chip (SOC) before real implementations are available; e.g., regarding interconnection schemes, application mapping, or the impact of new accelerator IP blocks.
By Erno Salminen and Lasse Lehtonen.
Both Erno Salminen and Lasse Lehtonen are with Tampere University of Technology, Finland.
Editor's Note: This article originally appeared in the April, 2012 issue of OCP-IP News.
Go to the OCP International Partnership (OCP-IP) website to learn more.
|Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, simulation, simulators, network-on-chip, NoC, on-chip interconnect, IP, intellectual property, cores, SystemC, OCP International Partnership (OCP-IP), SOCcentral,|