May 14, 2012 -- The Dynamic Random Access (DRAM) memory subsystem is a crucial component of a computing system architecture. The system performance largely relies on efficient memory accesses, and design decisions for the system architecture based on trustable memory models. However, current memory models used in system modeling and performance evaluation are far too simple.They respond to memory access requests either immediately, or with just a fixed delay. As a consequence, such over-simplistic models may mislead the design space exploration of system architectures. Over-optimistic performance data may be generated or wrong performance bottlenecks identified, leading to forced system re-architecting when realistic memory models are in place. Nevertheless, building accurate DRAM models are nontrivial, due to generations of a large variety of DRAM products having a wide range of timing-related constraints.
At the Network-on-Chip Benchmarking Working Group (NoC-BWG) of OCP-IP, we have launched efforts to target this challenge. The first effort is to define an accurate DRAM model specification , which captures the key timing and access-dependency parameters at the lowest level while, at the same time, keeping the abstraction level high enough to make the system development easy. The values of these parameters can be found in either the JEDEC (Joint Electron Device Engineering Council) specification  or the DDR model specification (for example, the Micron DDR model ). Based on these values, the memory model can produce transaction and history-specific latencies.
Based on , the NoC-BWG started the second effort, which is to design and implement an accurate high-level DRAM model in SystemC . A design project was defined by myself and launched at KTH. A team of four Masters students, Nan Li, Yi Wang, Huisheng Zhou and Lei Liang, worked on this project under my supervision. The outcome of this project resulted in the release of the ADM (Accurate DRAM Model in SystemC) package.
Figure 1. An overview of the ADM package. The accurate DRAM model consists of three major modules: a scheduler, a controller, and a core DRAM timing module.
It is the core timing module which takes into account the major delay parameters of a real DRAM, and imitates its timing behavior and access dependencies. The scheduler studies the impact of different scheduling polices, such as FIFO, round-robin and priority, upon the memory access performance. These scheduling polices can be seen as examples, and users may design more-advanced scheduling polices of their own within the structure. The controller is an interface between the scheduler and the core DRAM timing module. It is possible to combine the scheduler and the controller. However, the separation makes it easier to develop different scheduling functions tht may be desired by users.
As also shown in Figure 1, there is a test module provided in the ADM package. The test module generates transactions to test the DRAM performance while under test. It also functions as an example for how to hook user-designed modules into the accurate DRAM model. A demo program provided in the package can be used to test the delay and throughput of the DRAM for certain traffic flows.
The ADM provides a configurable, cycle-approximate, transaction-level timing model for realistic DRAMs.
Configurable - This means that the user can set different values for the parameters in order to mimic the timing behavior of different DRAMs. One can even configure the simple DRAM models (immediate or fixed-delay response) through the configuration.
Cycle approximate - For the scheduler and controller, the operations are cycle accurate, but for the DRAM timing model, it is cycle-approximate. As the latencies of DRAMs are expressed in nanoseconds, a higher DRAM speed means a larger approximated number of cycles. According to a given speed of the DRAM, a different number of cycles in delay is to be simulated.
Transaction-level - The model is written in SystemC using the OCP TLM Kit. Functions are implemented as function calls.
Integration friendly - The user can directly use or extend the scheduling function. The model can be combined with other OCP-compatible modules through an OCP TL1 interface. One can integrate one's own traffic generators and interconnect modules to the ADM.
The current ADM uses the following modeling packages: SystemC 2.2.0, TLM 2.0.1, and OCP TLM Kit 2.2x2.1. It has been tested under different platforms: 32-bit Linux Ubuntu 10.04 with gcc 4.4.3, 32-bit Linux Ubuntu 9.10 with gcc 4.4.1, 32-bit Windows XP Cygwin with gcc 4.3.4, and 64-bit Windows 7 Cygwin with gcc 4.3.4. For technical details of the design and implementation of the ADM, refer to .
New Accurate DRAM Memory Model Package Available!
OCP-IP's NoC Benchmarking Working Group announced the availability of an Accurate Dynamic Random-Access Memory Model (ADM) package. The ADM is a configurable, transaction-level model for Dynamic Random-Access Memories (DRAMs). This model is more accurate than current DRAM models used for system simulation because it considers the major delay parameters of real DRAMs and imitates their timing behavior with access dependencies captured. A demonstration program provided in the package can be used to test the delay and throughput of the DRAM for certain traffic flows, more-accurately representing the performance of systems and enabling a realistic evaluation of networks-on-chip (NOCs) deployed in those systems.
The model package was developed in SystemC using OCP-IP's TLM Kit. and can be combined with other OCP-compatible modules through an OCP TL1 interface.
The package is freely available to both OCP-IP members and non-members alike, through GNU LGPL licensing at www.ocpip.org/memory_model.php.
The Network on Chip Benchmarking Working Group has also issued an open call for Benchmarks to be distributed to researchers. NoC researchers may submit benchmarks from any application domain to be included. For more information on the call for benchmarks, please see www.ocpip.org/ocpspec_call_for_benchmarks.php.
 Krishnan Srinivasan and Erno Salminen. "A memory subsystem model for evaluating network-on-chip performance," OCP-IP white paper, September 2010.
 Joint Electron Device Engineering Council, JEDEC Specification.
 Micron Technology, Inc., Micron DDR2 specification
 Nan Li, Yi Wang, Huisheng Zhou and Lei Liang. "Design and Implementation of an Accurate Memory Subsystem Model in SystemC," Technical report, KTH. December 2010. (Available in the ADM package.)
By Zhonghai Lu
Zhonghai Lu is currently an associate professor directing the Dependable Autonomous Systems group at the Department of Electronic Systems, School of Information and Communication Technology at the Royal institute of Technology, KTI.
Editor's Note: This article originally appeared in the July, 2011 issue of OCP-IP News.
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