June 1, 2012 -- Much of the media focus and discussion within the semiconductor industry is related to mitigating design and manufacturing challenges at nanoscale process nodes. EDA providers continue to develop design tool flows to address these "bleeding-edge" SOC processors in 28-nm or 22-nm technology; with a price tag of several million dollars per license. What seem to be ignored are the thousands of innovative and important analog and mixed-signal ASIC designs that are being produced at mainstream process nodes such as 90nm and above.

There are thousands of mainstream analog and mixed-signal (A/MS) ASICs in mature process technologies, with volumes in the millions, being produced in foundries in Asia, Europe and elsewhere. These designs could include a few million gates in a 0.13- or 0.18-micron process running at a few hundred megahertz. Designers working at these mainstream process nodes can access a host of EDA tools targeting the design of mixed-signal ASICs that offer close to the same levels of functionality and performance. Backed up by access to foundry PDKs (process design kits), these tools offer productivity and cost-effectiveness. In fact, they are best-suited for designs at these nodes because they offer just the right level of capability and performance required to get the job done.

An historical challenge for designers looking for a toolset has been the somewhat bespoke nature of offerings. Finding a truly integrated and cohesive flow for A/MS has required paying a high price for a "big three" offering - - or having to assemble a flow from various point tools. Recent changes and collaborations within the EDA ecosystem are offering designers an alternative that provides the productivity and cohesiveness of an integrated flow with the price-performance mandated by today's competitive market pressures.

Tanner EDA, Aldec, Inc. and Incentia Design Systems, Inc. have collaborated to offer a complete A/MS design flow that is cohesive, efficient and competitively priced. The integrated offering, sold and supported by Tanner EDA as HiPer Silicon A/MS includes all of the requisite tools for driving from schematic capture to tape-out.

The design flow

Looking at a typical design flow (Figure 1) and starting with the digital steps, design entry can begin with Tanner EDA's S-Edit schematic editor. For digital simulation, the Riviera-PRO mixed-language RTL and gate-level simulator from Aldec is integrated directly into the Tanner solution.

It includes debugging and support of verification methodologies with SystemC and SystemVerilog, assertions-based verification (ABV), transaction-level modeling (TLM) and VHDL/ Verilog design rule checking (DRC). Analysis of the analog and digital elements comes together within the AMS Simulation cockpit; where the Designer can control and view runs and results from the T-Spice and Riviera-PRO tools.

Figure 1. An EDA ecosystem, built around tools from Tanner EDA, Aldec and Incentia Design Systems, offers a complete A/MS design flow that is cohesive, efficient and competitively priced.

For synthesis, a similar case can be made for cost-effective tools. In addition to providing basic synthesis functionality with the DesignCraft tool from Incentia, also on offer are a host of add-ons to make a world-class design flow. DesignCraft supports standard gate library formats and lets designers turn RTL code into gate-level VHDL or Verilog, and also offers the integrated capability to optimize for area, power, timing, and design-for-testability (DFT).

In addition, the Incentia timing and power- analysis and optimization tools are best-in-class tools, setting timing constraints and delivering power optimization at the synthesis level, which can lead to a significant reduction in consumption.

Digital place-and-route is a function that can be executed very efficiently in isolation. A gate-level netlist can be run through a place-and-route tool providing the physical layout and a timing file for re-simulation. Because the function is very portable, there are several efficient and economical options for design teams. If it's a modest requirement, then Tanner EDA has an excellent tool for basic place-and-route requirements, which is in the sub-100k-gate region and for circuits where timing-driven layout is not critical. A second option, if it's a more exacting requirement, is to use a design services company or the target foundry to provide this service. For two or three designs per year, this can be a very cost-effective approach, compared to buying an annual license for tools from the leading vendors.

Going back to the top of Figure 1, the analog design flow follows a traditional approach of schematic entry; simulation via Spice; and full-custom layout, although this may include some semi-automated tasks. It's typically necessary to iterate on the schematic entry and simulation loop a few times to ensure correct circuit operation. Following sign-off, the schematic design is passed through to analog layout, which automatically generates all the basic components in the schematic, so all the designer need do is the place-and-route.

Tanner's HiPer DevGen layout tool also features an advanced acceleration program that will identify and automatically generate key circuit elements with a wide range of additional constraint information, ensuring that any process-related effects are taken into account.

Top-level layout brings together the analog and digital in a single chip, with connectivity information extracted from the layout to verify correct performance. The post-layout analog and mixed-signal (AMS) co-simulation has the analog simulated in Spice and the digital simulated in the VHDL or Verilog simulator. HiPer Silicon A/MS provides the handshaking and management between the two domains.

Once circuit performance is established, full-chip verification is run including LVS (layout versus schematic) for both the analog and digital, top-level verification to ensure everything is connected correctly, and design rule checking (DRC) to confirm the chip is ready for manufacture at the target foundry. Once satisfied, the GDSII can be sent to the fab for final rule checking prior to tape-out.

By Paul Double

and John Zuk

Paul Double is the Founder and Managing Director of EDA Solutions. EDA Solutions is the European representative for Incentia, MOSIS and Tanner EDA.

John Zuk is the Vice President of Marketing and Business Strategy for Tanner EDA. John has extensive experience in creating new business models and launching new products and services within several high tech markets including semiconductors, automotive, and medical devices.