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 Category: SOCcentral Feature Articles & Columns: Feature Articles: Friday, April 25, 2014
Testing the 3D Waters  
Contributor: Mentor Graphics Corp.
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July 19, 2012 -- There certainly has been no lack of talk these days on the industry's eventual migration to 3D-ICs. No matter which conference you go to or which trade publication you read, you are bound to encounter some 3D-related material. All of this activity is understandable given the significant performance and power benefits the move to 3D provides. In fact, we already see a number of companies begin to test the 3D waters.

A number of devices making use of silicon interposers (often referred to as 2.5D devices) are currently being manufactured, and several devices consisting of memory die vertically stacked on a system-on-chip (SOC) using through-silicon vias (TSVs) are being designed. The move to vertically stacked logic die is not that far behind. However, there are still a number of challenges to solve and technologies to develop or refine to fully enable this migration. These challenges include both design automation as well as wafer-equipment-related issues.

One of the most often cited concerns relates to testing the 3D stacks. It turns out that the test problem is already pretty well covered and just requires proper choices to be made. Consider the two basic 3D-test requirements: 1) testing the individual die before they are stacked and 2) testing the stack assembly. Bare-die testing becomes far more critical with 3D stacks. With single-die packages, an improperly tested bare die will get caught during final package test. The only cost of not detecting the defective bare die during wafer-level testing is the wasted package.

In contrast, when assembling multiple die together in a vertical stack, a single defective die not only results in a wasted package but also forces all the good die in the stack to be discarded as well. What's worse is that the probability of having at least one defective die in a stack grows exponentially with the size of the stack. Detecting all defective die before stack assembly quickly becomes critical. This will require more comprehensive wafer-level testing. Much of this improvement can be achieved with existing advanced test techniques such as ATPG compression and various BIST solutions. Some investment is needed to develop and incorporate tests for portions of the design not typically covered during wafer test., such as mixed-signal circuits, high-speed I/Os and pre-bond TSVs.

Test of the stack assembly represents some new challenges. The first issue to resolve is whether to wait for the entire stack to be assembled before applying tests or to test each successive partial stack as each new die is added. This decision comes down simply to economics. The combined cost of the partial stack tests must be weighed against the cost of the fully assembled stacks that would be thrown away due to a defective die that was not detected earlier during the stacking process.

Another key challenge related to testing partial or full stacks is test access to the various die. In a 3D stack, typically only the bottom die has its I/Os bonded to the package pins. All other die are only connected to their direct neighbors (top or bottom) through TSV connections. Routing test data to and from any of these die requires some infrastructure for passing test data from one die to the next. In principle this is relatively straightforward; the challenge lies in the fact that a stack will generally contain die from different sources. Mechanisms for passing test data within each die must be compatible, so standardization is needed. Fortunately, the IEEE P1838 working group is currently developing such a standard. Once available, use of this standard in designs targeted for 3D will be critical. This may seem obvious, but getting standards adopted by design teams is often an uphill battle, especially when they affect performance or schedules.

Once access is available, testing the 3D stack is best performed using a hierarchical approach much the same way that large SOCs are now being tested. This divide-and-conquer methodology is the most-scalable approach. Each die in the stack is re-tested using the wafer (bare die)-level tests. The interfaces between the die consisting of TSVs and any related logic are then tested separately. Much of the automation necessary to generate these additional tests already exists, as hierarchical solutions developed for large SOCs are almost directly applicable to 3D stacks.

The adoption of 3D-ICs will surely unveil new test-related issues that will require new test features, but existing test solutions are good enough to let companies at least put their toes in the 3D waters, if not dive right in.


By Stephen Pateras

Stephen Pateras is product marketing director for Mentor Graphics Corp.'s Silicon Test products.

For more information, a whitepaper on 3D-IC Testing is available at the Mentor Graphics website.


Go to the Mentor Graphics Corp. website to learn more.

Keywords: ASICs, ASIC design, 3D ICs, 3D chips, stacked ICs, EDA, EDA tools, electronic design automation, packages, packaging, SOCcentral, Mentor Graphics,
488/38848 7/19/2012 2790 2790
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