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 Category: SOCcentral Feature Articles & Columns: Feature Articles: Sunday, May 03, 2015
Hybrid Prototyping Delivers the Best of Both Virtual and FPGA Prototyping to SOC Hardware and Software Teams  
Contributor: Synopsys, Inc.
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August 3, 2012 -- The complexity and cost of software development is impacting the timely introduction of new electronic system products, often undermining a product's market acceptance due to bugs that hide until after production. Recent industry surveys indicate that most chip-design projects are late and that spending on software development is outpacing hardware development. In fact, an estimated 70% of the engineering team for a 40-nm SOC design is involved with writing embedded software. To help address this design trend, virtual and hardware prototypes have emerged as a key enabler of pre-silicon software development and faster hardware/ software integration of complete systems.

Figure 1. Software- and hardware-development cost trends for different process nodes.

Virtual and FPGA-based prototypes are now actively used for firmware development, OS bring-up, driver development and various other kernel and user-space debug tasks. Prototypes assist in two key areas: software validation to confirm correct functional behavior, and system integration to confirm hardware and software operation. Design teams are realizing 9 to 12 months of schedule reduction by applying these advanced prototyping methodologies to their development processes.

Software-development teams are focusing on support for virtual prototyping with C++/ SystemC model abstractions of the system as well as FPGA-based PCB systems developed as a target for ASIC RTL. Given the ease of modeling a complex SOC block as a loosely timed (LT) SystemC representation versus the RTL-equivalent in Verilog HDL or VHDL, the virtual model has a clear time-to-model advantage (on the order of weeks versus months for the equivalent RTL version). In fact, for many common design blocks such as processor cores and chip interfaces, system-level models already exist and are readily available from the IP provider or a 3rd party. This enables the rapid development of virtual prototypes that have the required throughput for software bring-up.

Later in the project, when ASIC RTL is passing a significant amount of functional coverage (typically in the range of 60% to 80%), FPGA-based prototypes can be deployed. Developers using FPGA prototypes have the advantage of applying test equipment, pre-existing hardware subsystems and high-speed, cycle-accurate models to deliver a representation of the final chip with the highest interface fidelity and throughput. Some high-complexity processing engines, such as GPUs, demand high performance and cycle-accurate execution, making them well-suited for an FPGA prototype.

Because of the evolution of SOC prototyping and the unique expertise required to develop virtual and FPGA-based prototypes, the two methods have traditionally been implemented standalone. The abstracted C++/ SystemC models get developed and deployed very early in the project. After RTL for the blocks is available and stable, the FPGA systems are brought online. More recently, design engineers have recognized the compelling benefits of integrating the virtual prototyping and FPGA-based prototyping worlds.

For FPGA-prototype users, access to the virtual domain means:
  • Overall prototype capacity is increased.
  • IP blocks can be validated in the context of a CPU subsystem running actual embedded software.
  • Dependency on having final RTL is lowered.

Conversely, for engineers working in the virtual domain, access to high-speed, cycle-accurate hardware prototypes means:
  • A boost in prototype performance.
  • Modeling tasks become easier with access to real-world I/O and test equipment.
  • Pre-existing, proven legacy blocks (RTL) can be leveraged.

Synopsys recently introduced the first commercial "hybrid prototyping" solution that connects virtual and FPGA-based prototypes into a single environment. Synopsys' hybrid prototyping solution is based on Virtualizer, a tool set for the creation and execution of SystemC-based virtual prototypes, and HAPS, a scalable FPGA-based prototyping family with integrated prototyping software tools.

A hybrid prototype requires both a logical and physical link to combine the two types of prototypes. In Synopsys' hybrid prototyping solution, the physical link between the workstation host and HAPS system is accomplished using the Synopsys UMRBus Pod and a PCIe card adapter. The UMRBus (Universal Multi-Resource Bus) is a high-performance, low-latency communication channel between HAPS and an external host. It provides direct access to all pins, signals, nodes and registers within an FPGA. The synthesizable UMRBus RTL infrastructure is generated by the multi-FPGA prototyping software embedded in the HAPS systems.

For the logical link, Synopsys' Transactor Library for ARM AMBA enables the data exchange between SystemC/ TLM models executed by Virtualizer-based virtual prototypes and the HAPS-60 prototyping system. A general-purpose C++ transactor library with an application programming interface (API) is available for data-streaming applications or integration between a HAPS-60 system and custom C++ environments. In addition, SystemC transactors are available as Virtualizer model libraries, allowing the easy connection of the transactors with Virtualizer virtual prototypes. For the hardware domain, a synthesizable transactor IP core is introduced to the RTL design as an AMBA master or slave component, just like any other element on the SOC bus. The Synopsys Transactor Library supports a variety of AMBA protocols, including AMBA 2.0 AHB/APB, AXI 3 and AXI 4 ACE-Lite.

Figure 2. Conceptual representation of a transactor from Synopsys' Transactor Library for ARM AMBA.

Design teams that have adopted hybrid prototyping use various criteria to determine which SOC block will be assigned to a particular prototyping domain. Both the modeling effort and the attributes of the prototyping environment guide the modeling decision. A common convention is to assign complex processor cores and memory subsystems to the virtual domain to save FPGA hardware resources, benefiting from the high MIPS throughput and superior debug visibility.

When analog interfaces for optical or radio devices are attached to the prototype, the FPGA prototype add-on PCBs with analog PHYs provide the best performance with the high accuracy necessary to validate complex protocols or create new device drivers. With hybrid prototyping, system design teams can optimize their time-to-prototype availability by integrating existing RTL blocks and leverage virtual prototypes where a solution might not yet exist.

Figure 3. Comparison of FPGA and virtual prototyping, and their combined benefits.

As the software development effort in system design continues to grow, the cost and time to validate new SoC designs is becoming a significant bottleneck. Earlier software development directly translates into a time-to-market advantage for SoC and embedded systems developers. A hybrid prototyping solution leverages the merits of both virtual and FPGA-based prototypes to offer unparalleled software development productivity, including near real-time performance, connectivity to the analog domain, and higher debugging/analysis efficiency of multi-core systems.

By Troy Scott.

Troy Scott is a Product Marketing Manager responsible for FPGA-based prototyping software tools at Synopsys, Inc. He has 20 years of experience in the EDA and semiconductor industry. Before joining Synopsys, he was a product manager at Lattice Semiconductor, where he worked to design and market FPGA design tools. His background includes HDL synthesis and simulation, SOC prototyping and IP evaluation and marketing.

Editor's note: For more information on Synopsys' integrated hybrid prototyping solution, go to Synopsys Virtualizer.

Go to the Synopsys, Inc. website to learn more.

Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, virtual prototyping, FPGA-based prototyping, SOCcentral, Synopsys,
488/38917 8/3/2012 3613 3613
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