September 1, 2012 -- The worlds of system-on-chip (SOC) development and low-power design are almost completely intertwined these days. Most SOCs are developed for portable consumer devices where battery life can make or break a product. If the SOC is part of an implantable medical device, power consumption can make or break a patient. Even wall-powered systems may have to meet regulatory or market requirements for power consumption. It's a rare SOC project that doesn't need to use low-power-design techniques to some extent or another.

The most popular technique in low-power design is power shut-off (PSO) in which portions of the SOC not required for currently active functionality are powered off. This might appear to be a simple technique, but there are many ways to implement it incorrectly. A power-related bug is likely to require a chip re-spin to fix, so SOC teams are well-advised to take verification of their low-power designs seriously. This requires a combination of verification techniques, some well understood and some novel.

There are at least three categories of power-related signals within a low-power SOC. The first set actually turns the power on and off for different power domains with portions of the chip individually controllable. The second set controls the save and restore for any SOC state that must be retained during power-off. It's quite common to have specific registers or memory regions with critical data that must be available when power is restored. Finally, the outputs of powered-off domains must be isolated so that connected domains don't see incorrect values.

All three classes of signals — power, retention, and isolation — are produced by the power-control module (PCM), a state machine that controls the overall SOC power configuration. There is a bevy of important rules about how the signals are sequenced. For example, a power domain should not be turned back on until its retained state has been restored. Formal analysis can check these rules thoroughly, and other forms of design analysis can verify the low-power structures. An example would be confirmation that isolation cells are placed where needed.

But static analysis is not enough to verify proper low-power SOC operation. Ultimately, the verification team must ensure that the chip is still able to execute all functionality even when power domains are being turned off and on. There are several possibilities for how this can go wrong. For example, it may not be possible to awaken a power domain once it is turned off. It may turn out that some register or memory state should have been retained but was not, so that the power domain cannot pick up where it left off before the power-down.

Design errors can also occur between power domains. One domain may rely on signals from another domain that are isolated when powered down. The interaction between different portions of the chip means that effective low-power verification can only be performed at the full-chip level, when all power domains and PCM signals are visible. It is critical to run a wide range of functional tests while powering different portions of the SOC up and down while checking that results are unchanged by the low-power operation.

Modern simulators provide support for low-power verification, including setting all signals and un-retained states to unknown during a power-down. Although the Universal Verification Methodology (UVM) standard does not encompass low power, it has been adapted to work with simulation so that different power modes can be exercised as the UVM testbench is running functional tests. This works well at the module or sub-chip level, but as previously noted, only a subset of the low-power functionality can be verified.

At the full-SOC level, where all power domains are visible, UVM and other testbench approaches tend to break down. It becomes hard to exercise all of the chip's functionality from the chip inputs alone. This should not be surprising; in operation most of the SOC is controlled from the embedded processors. Hand-written tests running on these processors in a simulation can test some basic operations, but is it prohibitively difficult to manually write coordinated, multi-threaded tests running on multiple processors.

Given these limitations, it is hard in practice to run a wide range of full-chip tests — even without taking low-power design into consideration. Trying to manipulate power domains on top of the testbench is even more challenging. Again, this should not be surprising since low-power operation of the SOC is also largely controlled by the embedded processors. PowerWise and similar initiatives recognize that intelligent power-control decisions can be made only by system-level software aware of the running applications and their resource needs.

Fortunately, a solution is at hand. If the intended functionality of the SOC is captured in a set of hierarchical scenario models, verification software can automatically generate self-verifying C test cases that run on embedded processors in simulation. These test cases exercise the SOC, stressing design corner-case behavior more thoroughly than either hand-written tests or testbenches. The running test cases communicate with the chip I/O ports by reusing existing testbench components.

This solution can be extended to low-power verification by overlaying power-scenario models on top of SOC-scenario models. This crosses the system-level application scenarios with the options available for power control. The automatically generated test cases verify that the chip continues to operate as intended as power domains are turned on and off. A tool such as from Breker Verification Systems provides a solution for full-chip verification of both intended SOC functionality and low-power operation.

Given the near ubiquity of power-related structures in SOC designs, verification before tape-out is critical. Rather than relying on un-scalable testbenches, it's better to leverage the power of the SOC itself — its embedded processors — to verify low-power designs. This eliminates manual effort, reduces the time to tape-out, and makes it much more likely that the SOC will be able to move into production on first silicon.

By Thomas L. Anderson

Thomas L. Anderson is Vice President of Marketing for Breker Verification Systems, Inc. His previous positions include Product Management Group Director of Advanced Verification Systems at Cadence, Director of Technical Marketing in the Verification Group at Synopsys, Vice President of Applications Engineering at 0-In Design Automation, and Vice President of Engineering at Virtual Chips. Anderson has presented more than 100 conference talks and published more than 150 papers and technical articles on such topics as advanced verification, formal analysis, SystemVerilog, and design reuse.