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 Category: SOCcentral Feature Articles & Columns: Feature Articles: Sunday, December 21, 2014
Seeing Your IC Designs in 3D   Featured
Contributor: Mentor Graphics Corp.
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The semiconductor industry is rapidly moving towards deployment of FinFET transistors. These 3D devices are expected to provide important benefits such as lower static leakage leading to lower power ICs, and high drive currents enabling faster switching at lower supply voltages. FinFETs, however, represent a fundamental change to the underlying structure of the transistor, resulting in an impact on the IC design and manufacturing flows and corresponding automation tools.

The EDA industry is delivering new features and enhancements in the areas of physical design, physical verification, and parasitic extraction, as well as testing and failure analysis. Improvements range from automatic generation of fin geometries for physical verification, to new field-solver capabilities that compute the electrical field around the new 3D transistor geometries to achieve more accurate extraction of parasitics. Improvements in test and failure analysis are of particular importance as FinFET critical dimensions will be, for the first time, significantly smaller than the underlying node size. This has led to growing concern over increased defect levels and more yield challenges. Fortunately, EDA has made significant advancements in defect detection, diagnosis and yield analysis to address these challenges. Photo by Matt Neale, used under the Creative Commons Attribution.

One example is Cell-Aware test, a transistor-level test methodology that overcomes the limits of traditional stuck-at and transition fault models and associated test patterns by targeting specific shorts and opens internal to each standard cell, resulting in significant reductions in defect (DPM) levels. This technique can be used, for example, to specifically model and target leakage- and drive-strength-related transistor defects that are likely to be common in FinFET devices. The Cell-Aware approach requires only modest increases in test time despite significant improvements in defect coverage, making it a highly efficient and pragmatic solution.

The identification and correction of systematic defects is one of the few ways that fabless semiconductor companies can directly improve yield. Accurate and high-resolution diagnosis solutions already exist that can use test pattern failure data to determine a defect's most-probable failure mechanism and location. A more-advanced layout-aware diagnosis capability uses physical design layout information to further increase diagnostic accuracy and resolution, enabling identification down to a particular net polygon or a particular library cell instance. New capabilities are currently being developed to process failure results obtained from the applicationof Cell-Aware test patterns that will further improve resolution and provide transistor-level defect localization within the cell. Early research results already show successful correlation with physical failure analysis (PFA) results.

It is critical to separate random defects from those that are systematic so that PFA and other analysis efforts can be properly focused. Diagnosis-driven yield analysis is a methodology that leverages production-test results, volume defect-diagnosis results, and statistical analysis to identify root causes of yield loss.The methodology has been recently expanded to make use of design-for-manufacturing (DFM) data to further improve the yield-analysis results. In this new DFM-aware yield-analysis flow, the goal is to identify the DFM rules that best describe the actual design-process-induced systematic defects. This correlative analysis not only enables identifying problems with existing DFM rules, but it also helps identify new and unknown design features that may impact yield. This will no doubt prove very valuable as the manufacturing of FinFET-based designs begins to ramp up.

By Steve Pateras

Steve Pateras is Product Marketing Director within the Mentor Graphics Corp. Silicon Test Solutions Group and has responsibility for the company's ATPG and DFT products. He received his Ph.D. in Electrical Engineering from McGill University in Montreal, Canada. Steve can be reached at steve_pateras@mentor.com


Go to the Mentor Graphics Corp. website to learn more.

Keywords: ASICs, ASIC design, 3D ICs, 3D chips, stacked ICs, FinFET CMOS, EDA, EDA tools, electronic design automation, SOCcentral, Mentor Graphics
488/41459 6/6/2014 2011 2011
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