| Maximizing the Value of Your Internal IP |
May 15, 2013 -- Everyone today understands the essential importance of third-party semiconductor intellectual property (IP) to the health of the semiconductor industry. Considerably less attention is given to the importance of a strong, servicea ... read more |
| Yes, Virginia, There Is a Stitch-and-Ship |
April 5, 2013 -- Breker Verification System's Maheen Hamid recently published an article [1] warning about the dangers of the "stitch-and-ship" approach that some system-on-chip (SOC) teams employ. She discussed argument that if all the individu ... read more |
| Formal Verification Works Well for Connectivity Checking |
March 15, 2013 -- Connectivity checking — the verification of device wiring — is among the many unheralded, yet essential, tasks in ASIC design. In a nutshell, it's making sure that the connections between blocks of logic are correct. This ... read more |
| Verified Beyond Doubt |
March 14, 2013 -- What design team doesn't have the desire – make that goal – to have a chip that works as intended and taped out in just one spin? Come on. Let's be honest: They all do! Well then, let's focus on the methodology and tools to mee ... read more |
| Formal Verification and Validation |
March 14, 2013 -- I got my first demo of a formal verification tool in the spring of 1992. It was given by Paul Menchini of VHDL and other IEEE standards fame. No one could accuse Paul of not understanding the theory or not being familiar with C ... read more |
| A Call to Action: How 20nm Will Change IC Design |
February 8, 2013 -- The 20-nm process node promises performance, power and capacity breakthroughs that will allow electronics OEMs to provide the next generation of differentiated products. But the 20-nm node also raises significant new challeng ... read more |
| Demystifying Analog and Mixed-Signal ASICs |
February 8, 2013 -- Application specific integrated circuits, ASICs, typically conjure up the notion of massively complex logic chips containing tens or hundreds of thousands (even millions) of transistors configured to solve a customer's unique ... read more |
| Exposing the Hidden Costs of Using Off-the-Shelf Analog ICs |
January 14, 2013 -- With the demise of industry-wide second-sourcing and the move to developing purely proprietary designs, analog IC companies have raised the profit bar to new heights. Less affected than their digital brethren by the cyclical ... read more |
| The SOC Interconnect-Verification Challenge |
January 14, 2013 -- With increasing numbers of CPU cores, multimedia subsystems and communication IPs in today's systems-on-chips, the main SOC interconnects, crossbars or network-on-chip fabrics become key components of the system. In addition, ... read more |
| TLM-Driven Design and Verification: Time for a Methodology Shift |
January 7, 2013 -- While today's RTL design and verification flows are a step up from the gate-level flows of two decades ago, RTL flows are straining to meet the demands of most product teams. When designs are sourced and verified at the regist ... read more |
| Clock Domain Crossing Demystified |
January 2, 2013 -- The increase in SOC designs is leading to the extensive use of asynchronous clock domains. The clock-domain-crossing (CDC) interfaces are required to follow strict design principles for reliable operation. Also, verification o ... read more |
| RTL Analysis for Complex FPGA Designs Using a Grey Cell Methodology |
January 2, 2013 -- As designs are getting more complex, we are seeing two major issues that designers have to deal with in the RTL analysis space. The first issue has to do with sheer design size and the associated data volume. As designs go thr ... read more |
| Changing the Paradigm of Electrical Test |
January 2, 2013 -- The test of electronic circuits has been a key topic in the industry since the first transistor was developed, and today it is as relevant as ever. Test strategies are graded by how close they come to the ideal test solution w ... read more |
| Power and Thermal Modeling and Analysis of Multi-Die Packages |
December 17, 2012 -- Today's system designer has an unprecedented technology portfolio to conjure up the most-sophisticated, feature-rich designs for a variety of markets. But to produce designs that are competitive and meet or exceed customer e ... read more |
| Building Energy-Efficient ICs from the Ground Up |
December 5, 2012 -- Power consumption has moved to the forefront of digital-IC development as component sizes shrink and insulating layers on gates become thinner. To enable today's advanced low-power techniques, the design flow must holisticall ... read more |
| The Case for Developing Custom Analog SOCs |
December 3, 2012 -- Custom analog SOC (system-on-chip) designs are now a real option for many system houses and OEMs that previously found such designs outside their budgets. The reduction in fabrication costs for older-node processes (especial ... read more |
| 3D ICs with TSVs: Design Challenges and Requirements |
December 3, 2012 -- As demands accelerate for increasing density, higher bandwidths, and lower power, many IC design teams are looking to 3D ICs with through-silicon vias (TSVs). 3D ICs promise "more-than-Moore" integration by packing a great de ... read more |
| Blindsided by a Glitch |
November 19, 2012 -- The blindside blitz. The quarterback's greatest fear. The big hit that arrives with no warning and the cover bypassed. In SOC design, particularly in clock-domain-crossing (CDC) analysis, RTL designers can also believe they ... read more |
| Profiling Defect Sites for Yield Improvement |
November 9, 2012 -- While the industry progressively heads towards IC designs at 20nm and below, the challenges of profitably manufacturing these designs continue to emerge. As foundries confront the issues of manufacturing an acceptable yield, ... read more |
| New IJTAG Standard Simplifies SOC Verification and Test Processes |
November 5, 2012 -- Modern SOCs are a complex mix of embedded-IP cores, customized logic provided by the chip supplier and a myriad of communication interfaces. SOC designers have found that accessing instruments embedded into their chips and em ... read more |
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