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 Category: SOCcentral Feature Articles & Columns: Feature Articles: Sunday, May 24, 2015
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P2415: The New IEEE Power Standard for Unified Hardware Abstraction 

The current low-power design and verification standard (IEEE 1801-2013 and IEEE P1801) is focused on the voltage-distribution structure in design at register-transfer level (RTL) and below. It has minimal abstraction for time (having only an interval f ... read more

CDC Verification of Fast-to-Slow Clocks 

CDC checking of any asynchronous clock domain crossing requires that the data path and the control path be identified and that the receive clock domain data flow is controlled by a multiplexer with a select line that is fed by a correctly synchronized ... read more

Supporting Migration to Cloud Services and IoT: System-on-Chip Solutions 

December 8, 2014 -- In the past few years, there has been a sea change in terms of Internet accessibility, with service providers and equipment manufacturers driving wide deployment of broadband networks and access to the Internet, resulting in ... read more

Verification Contortions 

October 20, 2014 -- The verification tasks associated with debugging a chip design often seem like a job for a contortionist from Cirque du Soleil. Way too many of the verification engineers I know seem to contort their brains into pretzel-like ... read more

Deep Semantic and Formal Analysis: An Effective Tag Team for Static Verification 

September 8, 2014 -- A fundamental and secular change is underway in SOC verification. It is moving away from a tool-based to a verification-objective-driven mind set for design sign-off at the RT level. SOC companies are coming to rely on RTL s ... read more

Threading the Way through SOC Verification 

System-on-chip (SOC) projects have a gap between simulation testbenches and hardware-software co-verification in emulation or prototypes. Testbenches compliant with the Universal Verification Methodology (UVM) standard have no provision for running ver ... read more

Seeing Your IC Designs in 3D 

The semiconductor industry is rapidly moving towards deployment of FinFET transistors. These 3D devices are expected to provide important benefits such as lower static leakage leading to lower power ICs, and high drive currents enabling faster switchin ... read more

Progressive Static Verification Leads to Earlier and Faster Timing Sign-off 

January 22, 2014 -- As SOC design crosses the billion-gate threshold the cost of errors grows dramatically. The demand that engineers ensure their work is as correct as possible and as soon as possible in the design process has become more ... read more

Five Emerging DRAM Interfaces You Should Know About for Your Next Design 

December 30, 2013 -- Because dynamic random-access memory (DRAM) has become a commodity product, suppliers are challenged to continue producing these chips in increasingly high volumes while meeting extreme price sensitivities. It's no easy feat ... read more

Using Channel Coding to Verify and Increase the Performance of Channel-Coding Algorithms 

December 9, 2013 -- Low-density parity-check (LDPC) error-correcting algorithms are used to transmit messages over very noisy transmission channels. That ability makes them highly advantageous in high-speed digital communications technologies su ... read more

Design Flow, IP and Process Technology: Together at Last 

November 25, 2013 -- When ICs went into mass production over 50 years ago, the world was a very different place. Full-custom design and manufacturing know-how was concentrated in a few vertically integrated IDMs. With the shift to ASICs, the se ... read more

Who's Managing Your Power Management? 

September 30, 2013 -- Today's complex systems employ a wide variety of semiconductor technologies. From the deepest sub-nanometer processors to the analog I/O, it's easy to see the need for power management devices for 1.0V, 1.2V, 1.5V, 1.8V, 2. ... read more

Closing the Development Loop with Virtual Prototyping 

September 9, 2013 -- Abstraction has always been the primary facility for electronic systems design productivity. RTL is still the primary abstraction level for hardware design, but, because of slow simulation speeds and the difficulty to create ... read more

Environmentally Friendly Emulation without Compromises 

September 9, 2013 -- Since the dawn of EDA*, the business has been predominantly a software industry, with one notable exception. From the very beginning, the software-based design verification tools (primarily logic simulators) have been assist ... read more

Asymmetric Multiprocessing with Heterogeneous Architectures: Use the Best Tool for the Job 

September 6,2013 -- Often, the term "multiprocessing" is associated with tightly-coupled symmetric multiprocessing (SMP) architectures, due in large part to SMP's prevalence in high-performance computing, x86/x64 servers, and PCs. Unfortunately, ... read more

Reducing Power by Raising the Level of Abstraction 

May 30, 2013 -- It's well-known and accepted that decisions that have the most impact on power (or performance, for that matter) occur early in the design process at the architectural level. Some experts, such as Dr. Gary Delp at LSI, claim that ... read more

Increasing SOC Performance and Reducing Power Consumption through Memory Request Optimization 

May 29, 2013 -- Today's SOCs comprise many system clients; each contending for memory resources. Clients include multi-threaded/ multi-issue CPUs, high-end GPUs, video encode/ decode engines, and audio subsystems just to name a few. One of the S ... read more

A Comparison of OVM and UVM 

May 27, 2013 -- The Universal Verification Methodology (UVM) is a standardized hybrid methodology for verifying complex design in the semiconductor industry. It has superseded the Open Verification Methodology which was an Open Source verificati ... read more

The Many Faces of Low-Power Verification 

May 23, 2013 -- Power is a key factor in our beloved smartphones and tablets because they operate from a limited power source. Medical applications and automotive chips must account for power due to the thermal considerations in harsh or constra ... read more

The Next Roadblock to Custom-Design Productivity: Design Constraints 

May 21, 2013 -- Design constraints, which express design intent, are one of the pieces of ancillary data that are critical to the success or failure of a custom design. Design constraints aren't usually contained within layout files or library i ... read more

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