Page loading . . .

  
 Category: SOCcentral Feature Articles & Columns: Feature Articles: Monday, April 20, 2015
Sort Entries by    
Use the input form on the right to search on a word or phrase.  
Page(s): 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (315 Entries)
Staying On the Path to Moore’s Law Requires 3D Integration 

As the semiconductor industry struggles to maintain its momentum down the path of Moore’s Law, it is becoming clear that in addition to scaling line widths and chip sizes downward, some form of 3D IC integration will be necessary to achieve the interco ... read more

Strategies for Managing Data Across Multi-Site Design Projects 

August 5, 2009 -- In today’s global economy, many large engineering companies have design teams spread out all over the world, and these teams often collaborate on design and development projects. Managing multi-site projects is difficult ... read more

New Flow for Automating Verification of ESD Design Rules 

August 3, 2009 -- The high current of electrostatic discharge (ESD) pulses can cause severe damage to ICs, ranging from silicon and metal meltdown to gate oxide breakdown. With thinner oxides, thinner metals, shorter channel lengths, and multipl ... read more

Synthesis Needs to Change to Serve Modern Chip Design 

August 3, 2009 -- As EDA tools evolve, the resulting products try to increase automation. Unfortunately, the last great advance was from schematics to language-based design starting with the first synthesis tools in the mid-80’s. Designs have gr ... read more

Analog and Mixed-Signal IC Debug 

August 3, 2009 -- Increasing pressure on production costs and, more generally, time to market, have impacted all levels of IC design. In this context, one of the major challenges is to avoid silicon failure or yield loss. Failure costs are obvio ... read more

Emulation Finds Its Role 

July 15, 2009 -- It’s taken 25 years or longer, but I’m here to report that emulation platforms finally have become the key component to almost all engineering teams’ verification flows. It’s about time, wouldn’t you say? After all, verification ... read more

Layout Automation for the Next Generation of Custom Chips 

July 6, 2009 -- Like most steps in the IC design flow, custom layout is becoming more tedious, complex and time consuming. To keep up with increasing die size, tight time-to-market requirements and new process-induced layout constraints, automat ... read more

Reducing IC Power Consumption with Advanced Place-and-Route  

June 22, 2009 -- The growing pressure to reduce package cost and the extend battery life of consumer products in a highly competitive market has positioned IC power consumption as a key design goal at 45/32-nm technology nodes. However, the comp ... read more

Design and Verification Techniques for Clock Gating 

May 21, 2009 -- The demand for mobile consumer device has made power management the number one consideration in today’s system design. To increase battery life, system designers adopt aggressive power management techniques which includes multi v ... read more

Leveraging Standards When Times Are Tough 

February 16, 2009 -- During tough economic times, the instinct of many companies can be to cut back on their commitment to standards groups and industry organizations. This can inhibit the organization’s ability to deliver the most value to memb ... read more

FPGA-to-ASIC Conversion 

January 16, 2009 -- As FPGAs increase in both size and performance, they also naturally increase in complexity and price. Forward-looking FPGA users hope that their products will take off, driving demand for higher volumes. They consider from th ... read more

Casey at the Bat 

Editor's Note: One way to describe what's happened to the economy, the congress and the administration is that they've all "struck out." This reminded us of the great baseball poem penned by Ernest Lawrence Thayer way back in June, 1888. If you're n ... read more

Designing for State Retention 

December 12, 2008 -- Consumers judge battery-powered products by both their standby life – how long the device lasts between battery charges – and how responsive they are when actively used. Both the sub-threshold and gate-leakage power componen ... read more

Single, Unified Datamodel Key to Integrated IC Implementation Flow 

November 6, 2008 -- In nanometer designs, performance, power, area, signal integrity, yield, packaging and, in fact, all design issues are inextricably intertwined. As a result, they cannot be addressed adequately by implementation flows made up ... read more

Challenges in 45-nm Physical Design 

November 6, 2008 -- With each new generation of ICs, previously manageable challenges in physical implementation emerge as extremely disruptive discontinuities. In response, new generations of design tools become necessary to realize the benefit ... read more

Deep Submicron Designs Challenge Physical Implementation Tools 

November 6, 2008 -- As process geometries shrink to 45nm and below, every phase of the design cycle is affected. This is most evident at the physical implementation stage, where floorplanning, placement, routing and optimization must be fine-tun ... read more

Test Structures Make Designs Harder to Verify 

October 28, 2008 -- The addition of test structures, whether they're scan chains or built-in test circuitry for at-speed testing of fabricated designs, means additional steps need to be taken in the IC design stage to ensure correct operation of ... read more

Perfect Storm Brewing for Chip and Circuit Board Test 

October 22, 2008 -- Maybe it’s not as dramatic as a tsunami, but it sure seems like a perfect storm is brewing for chip and circuit board test because of factors such as the effects of sub-100-nm chip fabrication processes, the capacitance anoma ... read more

When Silicon Processes Shrink, Test Needs Expand 

October 6, 2008 -- As process nodes shrink below 90nm, the importance of test increases dramatically. Smaller feature sizes mean more gates, which translates to the need for more test structures and increased manufacturing tests. Problem is, tes ... read more

Electrical Fuse Makes Repairable Memory Testing Easy 

October 6, 2008 -- According to the International Technology Roadmap for Semiconductors 2007 [1], the percentage of memory in CPU cores ranges from 65 to 75% and from 83 to 86% in consumer cores. For an SOC design, memory density is higher than ... read more




 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Executive
Viewpoint

Verification Contortions


Dr. Lauro Rizzatti
Verification Consultant
Rizzatti, LLC

Real Talk

P2415: The New Power Standard for Unified Hardware Abstraction


Graham Bell
VP Marketing
Real Intent

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Tutorials, Whitepapers & App Notes
Archived Webcasts
Newsletters



About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
553.488  0.28125