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 Category: SOCcentral Feature Articles & Columns: Feature Articles: Saturday, August 30, 2014
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Emulation Finds Its Role 

July 15, 2009 -- It’s taken 25 years or longer, but I’m here to report that emulation platforms finally have become the key component to almost all engineering teams’ verification flows. It’s about time, wouldn’t you say? After all, verification ... read more

Layout Automation for the Next Generation of Custom Chips 

July 6, 2009 -- Like most steps in the IC design flow, custom layout is becoming more tedious, complex and time consuming. To keep up with increasing die size, tight time-to-market requirements and new process-induced layout constraints, automat ... read more

Reducing IC Power Consumption with Advanced Place-and-Route  

June 22, 2009 -- The growing pressure to reduce package cost and the extend battery life of consumer products in a highly competitive market has positioned IC power consumption as a key design goal at 45/32-nm technology nodes. However, the comp ... read more

Design and Verification Techniques for Clock Gating 

May 21, 2009 -- The demand for mobile consumer device has made power management the number one consideration in today’s system design. To increase battery life, system designers adopt aggressive power management techniques which includes multi v ... read more

Leveraging Standards When Times Are Tough 

February 16, 2009 -- During tough economic times, the instinct of many companies can be to cut back on their commitment to standards groups and industry organizations. This can inhibit the organization’s ability to deliver the most value to memb ... read more

FPGA-to-ASIC Conversion 

January 16, 2009 -- As FPGAs increase in both size and performance, they also naturally increase in complexity and price. Forward-looking FPGA users hope that their products will take off, driving demand for higher volumes. They consider from th ... read more

Casey at the Bat 

Editor's Note: One way to describe what's happened to the economy, the congress and the administration is that they've all "struck out." This reminded us of the great baseball poem penned by Ernest Lawrence Thayer way back in June, 1888. If you're n ... read more

Designing for State Retention 

December 12, 2008 -- Consumers judge battery-powered products by both their standby life – how long the device lasts between battery charges – and how responsive they are when actively used. Both the sub-threshold and gate-leakage power componen ... read more

Single, Unified Datamodel Key to Integrated IC Implementation Flow 

November 6, 2008 -- In nanometer designs, performance, power, area, signal integrity, yield, packaging and, in fact, all design issues are inextricably intertwined. As a result, they cannot be addressed adequately by implementation flows made up ... read more

Challenges in 45-nm Physical Design 

November 6, 2008 -- With each new generation of ICs, previously manageable challenges in physical implementation emerge as extremely disruptive discontinuities. In response, new generations of design tools become necessary to realize the benefit ... read more

Deep Submicron Designs Challenge Physical Implementation Tools 

November 6, 2008 -- As process geometries shrink to 45nm and below, every phase of the design cycle is affected. This is most evident at the physical implementation stage, where floorplanning, placement, routing and optimization must be fine-tun ... read more

Test Structures Make Designs Harder to Verify 

October 28, 2008 -- The addition of test structures, whether they're scan chains or built-in test circuitry for at-speed testing of fabricated designs, means additional steps need to be taken in the IC design stage to ensure correct operation of ... read more

Perfect Storm Brewing for Chip and Circuit Board Test 

October 22, 2008 -- Maybe it’s not as dramatic as a tsunami, but it sure seems like a perfect storm is brewing for chip and circuit board test because of factors such as the effects of sub-100-nm chip fabrication processes, the capacitance anoma ... read more

When Silicon Processes Shrink, Test Needs Expand 

October 6, 2008 -- As process nodes shrink below 90nm, the importance of test increases dramatically. Smaller feature sizes mean more gates, which translates to the need for more test structures and increased manufacturing tests. Problem is, tes ... read more

Small Delay Defect Testing 

October 6, 2008 -- Small delay defects occur in all manufacturing processes. What makes them "small" is not their absolute size so much as the fact that they’re small relative to the timing margins allowed by the maximum operating frequenc ... read more

Electrical Fuse Makes Repairable Memory Testing Easy 

October 6, 2008 -- According to the International Technology Roadmap for Semiconductors 2007 [1], the percentage of memory in CPU cores ranges from 65 to 75% and from 83 to 86% in consumer cores. For an SOC design, memory density is higher than ... read more

Comparing an IP-Centric DDR Solution with a System-Centric DDR Solution for Improved System Performance 

September 8, 2008 -- The design of modern electronics equipment is a difficult balancing act. The need for fast time-to-market, high-performance, differentiation of advanced features, low-cost, and low-power bear down heavily on designers and a ... read more

Solving the DFM Interoperability Crisis 

September 2, 2008 -- The semiconductor industry has long recognized the growing issues of manufacturability and wider parameter variations at the deep, sub-micron process nodes. Many EDA startups that developed capable DFM point tools, which foc ... read more

The Shifting Landscape of DFM 

September 2, 2008 -- The term design for manufacturability (DFM) means different things to different audiences. From a practical standpoint, DFM represents the communications between the design community and the manufacturing community to ensure ... read more

A Comprehensive Approach to Manufacturing Variability 

September 2, 2008 -- A growing challenge for IC designers at advanced process nodes is controlling manufacturing variability during the design. Variability in manufacturing is emerging as a leading cause for chip failures and delayed schedules, ... read more




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