| Single, Unified Datamodel Key to Integrated IC Implementation Flow |
November 6, 2008 -- In nanometer designs, performance, power, area, signal integrity, yield, packaging and, in fact, all design issues are inextricably intertwined. As a result, they cannot be addressed adequately by implementation flows made up ... read more |
| Test Structures Make Designs Harder to Verify |
October 28, 2008 -- The addition of test structures, whether they're scan chains or built-in test circuitry for at-speed testing of fabricated designs, means additional steps need to be taken in the IC design stage to ensure correct operation of ... read more |
| Perfect Storm Brewing for Chip and Circuit Board Test |
October 22, 2008 -- Maybe it’s not as dramatic as a tsunami, but it sure seems like a perfect storm is brewing for chip and circuit board test because of factors such as the effects of sub-100-nm chip fabrication processes, the capacitance anoma ... read more |
| When Silicon Processes Shrink, Test Needs Expand |
October 6, 2008 -- As process nodes shrink below 90nm, the importance of test increases dramatically. Smaller feature sizes mean more gates, which translates to the need for more test structures and increased manufacturing tests. Problem is, tes ... read more |
| Electrical Fuse Makes Repairable Memory Testing Easy |
October 6, 2008 -- According to the International Technology Roadmap for Semiconductors 2007 [1], the percentage of memory in CPU cores ranges from 65 to 75% and from 83 to 86% in consumer cores. For an SOC design, memory density is higher than ... read more |
| Small Delay Defect Testing |
October 6, 2008 -- Small delay defects occur in all manufacturing
processes. What makes them "small" is not their absolute size so much as the
fact that they’re small relative to the timing margins allowed by the maximum
operating frequenc ... read more |
| Comparing an IP-Centric DDR Solution with a System-Centric DDR Solution for Improved System Performance |
September 8, 2008 -- The design of modern electronics equipment is a difficult balancing act. The need for fast time-to-market, high-performance, differentiation of advanced features, low-cost, and low-power bear down heavily on designers and a ... read more |
| The Shifting Landscape of DFM |
September 2, 2008 -- The term design for manufacturability (DFM) means different things to different audiences. From a practical standpoint, DFM represents the communications between the design community and the manufacturing community to ensure ... read more |
| A Comprehensive Approach to Manufacturing Variability |
September 2, 2008 -- A growing challenge for IC designers at advanced process nodes is controlling manufacturing variability during the design. Variability in manufacturing is emerging as a leading cause for chip failures and delayed schedules, ... read more |
| … But Will It Work? |
September 2, 2008 -- After the arduous design tasks of formal verification, consideration of statistical process variations, optimization of yield, and eventually careful fabrication of an SOC with a device size smaller than the wavelength of li ... read more |
| Manufacturing Concerns Move Up the Design Cycle |
September 2, 2008 -- The expression "design-for-manufacturing" (DFM) has been bandied about for so long, that designers regard it with suspicion. They've been told many times that shrinking process nodes will force them into a realm that was onc ... read more |
| Solving the DFM Interoperability Crisis |
September 2, 2008 -- The semiconductor industry has long recognized the growing issues of manufacturability and wider parameter variations at the deep, sub-micron process nodes. Many EDA startups that developed capable DFM point tools, which foc ... read more |
| Combining Metrics from Simulation and Formal |
August 5, 2008 -- There has been considerable talk recently about the desire to have a unified coverage metric that could combine both formal verification and dynamic verification. In addition, Accellera is pursuing an effort to create a standar ... read more |
| Formal Verification Goes Mainstream |
August 5, 2008 -- Formal verification is a term that's been kicking around the EDA industry for years, but only recently has seen some success in helping designers verify their complex SOC's, processors and ASICs. When it was first introduced, f ... read more |
| What Ever Happened to Formal Verification? |
August 5, 2008 -- Formal verification is defined by Wikipedia as "… the act of proving or disproving the correctness of intended algorithms underlying a system with respect to a certain formal specification or property, using formal methods of m ... read more |
| What Hardware Designers Need to Know About Systemverilog Testbench Debug and Analysis |
August 5, 2008 -- Shrinking silicon geometries enable larger SoC-type designs in terms of raw gate size, and many of today's applications take advantage of this trend. An important point that is often missed is the accompanying growth in verifi ... read more |
| Meeting Serial Rapid IO Architectural Trends in 3.5G and 4G Base Stations |
July 28, 2008 -- The architectures in next-generation 3.5G and 4G base stationsbase demand high-bandwidth backplanes for multiple baseband cards. In turn, the baseband cards require clusters of multicore digital signal processors (DSPs) for high ... read more |
| Art Imitating Life: Hardware Development Imitating Software Development |
July 21, 2008 -- I suspect my comments may offend a few hardware engineers and probably a bunch of software engineers, so I’ll apologize in advance for that. OK, with that out of the way, I can’t help but notice two interesting phenomena that h ... read more |
| Power Has Consequences, So Chill Out! |
June 9, 2008 -- The March edition of Vanity Fair had an article that covered Google’s construction of a three-building data center next to the Columbia River in Oregon, to take advantage of cheap power no longer required by a defunct alum ... read more |
| Low Power Is Now a High Priority |
June 9, 2008 -- Over the past several years, low-power design has crept up the list of engineers’ concerns and nestled right alongside timing as a major design objective. Several factors are driving low power’s ascent. The explosion in the popul ... read more |
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