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 Category: SOCcentral Feature Articles & Columns: Feature Articles: Friday, October 31, 2014
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The Shifting Landscape of DFM 

September 2, 2008 -- The term design for manufacturability (DFM) means different things to different audiences. From a practical standpoint, DFM represents the communications between the design community and the manufacturing community to ensure ... read more

A Comprehensive Approach to Manufacturing Variability 

September 2, 2008 -- A growing challenge for IC designers at advanced process nodes is controlling manufacturing variability during the design. Variability in manufacturing is emerging as a leading cause for chip failures and delayed schedules, ... read more

… But Will It Work? 

September 2, 2008 -- After the arduous design tasks of formal verification, consideration of statistical process variations, optimization of yield, and eventually careful fabrication of an SOC with a device size smaller than the wavelength of li ... read more

Manufacturing Concerns Move Up the Design Cycle 

September 2, 2008 -- The expression "design-for-manufacturing" (DFM) has been bandied about for so long, that designers regard it with suspicion. They've been told many times that shrinking process nodes will force them into a realm that was onc ... read more

What Ever Happened to Formal Verification? 

August 5, 2008 -- Formal verification is defined by Wikipedia as "… the act of proving or disproving the correctness of intended algorithms underlying a system with respect to a certain formal specification or property, using formal methods of m ... read more

Formal Verification Goes Mainstream 

August 5, 2008 -- Formal verification is a term that's been kicking around the EDA industry for years, but only recently has seen some success in helping designers verify their complex SOC's, processors and ASICs. When it was first introduced, f ... read more

What Hardware Designers Need to Know About Systemverilog Testbench Debug and Analysis 

August 5, 2008 -- Shrinking silicon geometries enable larger SoC-type designs in terms of raw gate size, and many of today's applications take advantage of this trend. An important point that is often missed is the accompanying growth in verifi ... read more

Combining Metrics from Simulation and Formal 

August 5, 2008 -- There has been considerable talk recently about the desire to have a unified coverage metric that could combine both formal verification and dynamic verification. In addition, Accellera is pursuing an effort to create a standar ... read more

Meeting Serial Rapid IO Architectural Trends in 3.5G and 4G Base Stations 

July 28, 2008 -- The architectures in next-generation 3.5G and 4G base stationsbase demand high-bandwidth backplanes for multiple baseband cards. In turn, the baseband cards require clusters of multicore digital signal processors (DSPs) for high ... read more

Art Imitating Life: Hardware Development Imitating Software Development 

July 21, 2008 -- I suspect my comments may offend a few hardware engineers and probably a bunch of software engineers, so I’ll apologize in advance for that. OK, with that out of the way, I can’t help but notice two interesting phenomena that h ... read more

Power Has Consequences, So Chill Out! 

June 9, 2008 -- The March edition of Vanity Fair had an article that covered Google’s construction of a three-building data center next to the Columbia River in Oregon, to take advantage of cheap power no longer required by a defunct alum ... read more

Low Power Is Now a High Priority 

June 9, 2008 -- Over the past several years, low-power design has crept up the list of engineers’ concerns and nestled right alongside timing as a major design objective. Several factors are driving low power’s ascent. The explosion in the popul ... read more

Multi-Corner, Multi-Mode Power Closure: The New Dimension in IC Design 

June 9, 2008 -- One of the biggest challenges in pushing IC design beyond 65nm is the complexity inherent in effective power management. Whether the goal is to reduce on-chip power dissipation to reduce temperature and minimize cooling requireme ... read more

Automating Advanced Low-Power Multi-Voltage Design 

June 9, 2008 -- Balancing power against performance has traditionally been a strategic decision, made during the design stage and implemented at the component level. Use of this power/ performance trade-off to differentiate one product from a pr ... read more

Industry Leaders Define Next Priorities for Low Power 

June 9, 2008 -- Once considered a veritable "black art" practiced only by voodoo cults (and advanced microprocessor designers), low-power design methodology has become a mainstream requirement for modern IC design. Initially, basic clock-gating ... read more

Beyond IR Drop: Dynamic Voltage Droops and Total Power Integrity 

May 22, 2008 -- Most system power delivery designers are intimately familiar with concepts of power network impedance, bypass or decoupling capacitor frequency responses, and the important roles played by device electrical aspects such as effect ... read more

ESL Is Finally Ready for Prime Time 

May 12, 2008 -- If you talk to vendors of electronic system-level (ESL) design tools, you’ll find that many have a unique approach to this evolving technology. Some vendors talk of virtual platforms, others focus on synthesis and simulation, and ... read more

Standardization Opens Virtual Platforms to Mainstream Use 

May 12, 2008 -- During the past three decades, the mainstream design entry for semiconductor-design has steadily evolved from layout, to transistors, to gates, and, most recently, to the register-transfer level (RTL). Each time the complexity a ... read more

SystemVerilog Modeling Guidelines to Avoid Synthesis- Simulation Mismatches 

April 28, 2008 -- Due to the increased complexity of recent designs, synthesis-simulation mismatches have become one of the most significant design issues during the verification phase. Most of the time, these mismatches are detected after silic ... read more

A Power Integrity Wall Follows the Power Wall! 

March 25, 2008 -- A decade ago, the call of the times was for solutions to address the "Power Wall," at least at leading microprocessor institutions. Conferences discussed looming challenges with supply currents exceeding thousands of amperes, a ... read more




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