| Standardization Opens Virtual Platforms to Mainstream Use |
May 12, 2008 -- During the past three decades, the mainstream design entry for semiconductor-design has steadily evolved from layout, to transistors, to gates, and, most recently, to the register-transfer level (RTL). Each time the complexity a ... read more |
| ESL Is Finally Ready for Prime Time |
May 12, 2008 -- If you talk to vendors of electronic system-level (ESL) design tools, you’ll find that many have a unique approach to this evolving technology. Some vendors talk of virtual platforms, others focus on synthesis and simulation, and ... read more |
| SystemVerilog Modeling Guidelines to Avoid Synthesis- Simulation Mismatches |
April 28, 2008 -- Due to the increased complexity of recent designs, synthesis-simulation mismatches have become one of the most significant design issues during the verification phase. Most of the time, these mismatches are detected after silic ... read more |
| A Power Integrity Wall Follows the Power Wall! |
March 25, 2008 -- A decade ago, the call of the times was for solutions to address the "Power Wall," at least at leading microprocessor institutions. Conferences discussed looming challenges with supply currents exceeding thousands of amperes, a ... read more |
| Customizable Processors |
March 11, 2008 -- In generic 130-nm and 90-nm standard-cell foundry process, silicon density routinely exceeds 100K to 200K usable gates per mm˛. Consequently, a low-cost chip (measuring 50mm˛) can carry 5M to 10M gates of logic. Simply because ... read more |
| Development of Embedded DSP Communications Algorithms for Software Defined Radio |
January 23, 2008 -- Use of Software Defined Radios (SDRs) has been steadily increasing due to the rapid improvements in embedded DSP horsepower and the high levels of integration possible in state-of-the-art FPGA devices. These improvements, cou ... read more |
| Power Integrity and Energy-Aware Floorplanning |
January 16, 2008 -- We've heard so much about floorplanning for integrated circuits – routing, timing awareness, and even leakage and temperature awareness – but how often do we come across the term "roof planning" in SOC's? Yet, just as the fou ... read more |
| Parasitic Extraction Challenges for Designing Advanced Process ICs |
January 9, 2008 -- The continual shrinking of IC transistor sizes and the market demand for systems-on-chip (SOC) solutions has resulted in more components on an IC along with larger die sizes. Designers are working with smaller device features ... read more |
| Parasitics Move Model Order Reduction into Electronic Design Automation |
January 3, 2008 -- Designing a system-on-chip (SOC) and delivering it on time and functional is a challenge and requires a lot of engineering to squeeze the most out of the technology. Today, 40% of design starts are SOCs. In a few y ... read more |
| Creating a Unified Power Flow |
November 12, 2007 -- Power has become a buzz-word among chip designers around the world. Everywhere there is a need to conserve power: battery-powered devices need to increase battery-life; workstations need to reduce cooling costs.
There ... read more |
| Applying Volume Diagnostics to Accelerate Yield Learning |
November 5, 2007 -- Though yield learning has been applied for
generations of semiconductor process technologies to improve product yields and
profits, the techniques both available and in use today are rapidly expanding. First, t ... read more |
| Silicon Validation via LFD Simulation |
August 6, 2007 -- Razrs, Krazrs, Blackberries, iPhones. Cars that park themselves, tell you when they need servicing and show you the fastest route to your destination. Consumers today, particularly electronics consumers, are demanding products ... read more |
| An Introduction to the VMM Register Abstraction Layer |
July 30, 2007 -- Modern SOC, ASIC and FPGA designs often have hundreds or even thousands of on-chip registers that are used to configure the device for different modes of operation. These memory elements play a critical role in the proper functi ... read more |
| Statistical Timing Analysis: Sign-off for a New Generation |
July 19, 2007 -- For the last couple of years, there has been extensive discussion about the use of statistical static timing analysis (SSTA) in the verification of current and future generations of IC designs manufactured at 90nm or below. Give ... read more |
| Simultaneous Multi-Scenario Timing Optimization for High-Performance Digital IC Designs |
July 12, 2007 -- When manufactured and deployed in the real world, digital ICs must operate across a range of temperatures and voltages, yield across all of the possible manufacturing process corners, and work in various functional modes for the ... read more |
| Process Variations Require Integrated Sign-Off Solutions |
July 6, 2007 -- In the traditional ASIC design flow, the sign-off stage was a key, well-defined point in the chip-making process. The designers would complete their front-end design and gate-level implementation, run timing sign-off using a stat ... read more |
| Why High MHz Does Not Mean High Performance |
May 31, 2007 -- Over the past several years, AMD has successfully fought the PR battle with Intel to convince OEMs, PC manufacturers, and consumers that frequency or megahertz (MHz) is not the right metric when evaluating the performance of proc ... read more |
| Selecting the Optimum ASIC Technology for Your Design |
May 1, 2007 -- Traditionally, designers had to choose between field programmable gate arrays (FPGAs) and standard cell technology for their projects. Alternative ASIC technologies are available and this article explains the characteristics and t ... read more |
| Where Do Structured ASICs Fit? |
May 1, 2007 -- Since 2006, there’s been a lot of skepticism surrounding the life (and potential death) of structured ASICs. Most of this skepticism comes from the fact that some suppliers have discontinued the products and others have de-emphas ... read more |
| Catapulting Fabless Start-Ups |
April 24, 2007 -- The semiconductor industry has always grown on waves of innovation, and much of this innovation has come from fabless start-ups. The top ten fabless semiconductor companies by revenue got to their positions by pioneering in the ... read more |
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