April 24, 2007 -- The semiconductor industry has always grown on waves of innovation, and much of this innovation has come from fabless start-ups. The top ten fabless semiconductor companies by revenue got to their positions by pioneering in the ... read more

April 20, 2007 -- For most system-on-chip (SOC) projects, software dominates development costs and market risk. Consequently, co-design should be biased towards software-centric methodologies. No SOC project starts from a blank page. Pressure to ... read more

April 9, 2007 -- Transaction-level modeling has been touted to considerably improve productivity in system-on-chip design. Recently, many popular SOC development environments have been flavored with the spirit of TLM, typically based on the favo ... read more

April 2, 2007 -- System-on-chip (SOC) verification has become more complex than ever as applications converge to offer more features for consumer products. This new level of complexity is presenting SOC development teams with many challenges inc ... read more

March 1, 2007 -- With the increased time, cost, and quality pressures on the development of electronic devices, software developers are faced with the challenge of reducing their dependency on the availability of a physical board. Such dependenc ... read more

February 26, 2007 -- Despite warnings of dire consequences and tales of chips not fitting their packages, not nearly enough attention has been paid to IC package and chip co-design. And, I'm inclined to believe that this will persis ... read more

February 2, 2007 -- Hundreds, if not thousands, of articles have been written to discuss the “verification crisis” for system-on-chip (SOC) designs. The crisis is real: many studies have shown that two or three very expensive silicon iterations ... read more

February 2, 2007 -- SystemVerilog Assertions (SVA) constitute a major language feature of the IEEE Std. 1800-2005 SystemVerilog standard. Local variables are a powerful component of SVA that allow the sampling and manipulation of data in a prope ... read more

January 8, 2007 -- As chip designs migrate down the process roadmap from 130 to 90 to 65nm and beyond, the cost of implementing a system-on-chip (SOC) solution doubles to triples at each smaller process node. For example, at 130-nm a typical hig ... read more

January 8, 2007 -- The course of electronic systems design changed irreversibly on November 15, 1971 when Intel introduced the first commercial microprocessor, the 4004. Before that date, system design consisted of linking many hardwired blocks, ... read more

November 13, 2006 -- Testing advanced communication devices can pose significant challenges. The move to higher circuit densities, with various on-chip functionalities, introduces a broad set of challenges for manufacturing test. Further complic ... read more

October 23, 2006 -- Ask SOC designers to name the biggest problems they face and, invariably, timing closure and power dissipation are at the top of the list. There are several reasons for the existence of these problems, including increasing d ... read more

October 23, 2006 -- The challenge of on-chip communication traffic is presently compounded in two ways: First, use of multiple processors and cores with single or multiple memories in system-on-chips (SOCs) are driving the need for a lower cost, ... read more

October 17, 2006 -- The trend to combine multiple functions on one piece of silicon to reduce cost, power consumption, and manufacturing and test time is gathering momentum, driven by requirements for smaller, less expensive high performance pro ... read more

September 25, 2006 -- “Wait a minute; don’t forget to add the memory.” How often did we hear that phrase in the design labs of the 1980s and early 1990s? Back then, the DRAM industry was such that Henry Ford himself would have been proud to be ... read more

August 28, 2006 -- Compared with FPGAs, structured ASICs provide more performance, lower per-unit cost and lower power consumption. This device class operates much like an application-specific ASIC or FPGA, using pre-diffused blocks coupled with ... read more

August 10, 2006 -- Developing integrated circuits at 130, 90 and 65 nanometers is a risky and expensive business but rewarding when the design is successfully implemented. Now more than ever, developers of complicated system- on-chip (SOC) desig ... read more

August 10, 2006 -- Semiconductor memory companies originally used the concept of laser fuses along with redundant rows and columns to boost yield. While most memory chips continue to use fuses, the concept has spread to several aspects of chip d ... read more

July 14, 2006 -- Design for manufacturing (DFM) has received increasing levels of attention at DAC since 1999, and very noticeably so since 2003. Since the term DFM was coined about a decade (or more) ago, its definition has been modified accor ... read more

July 14, 2006 -- The IEEE has recently ratified SystemVerilog and SystemC to be official IEEE standards known as IEEE Std. 1800-2005 and IEEE Std. 1666-2005 respectively. This step is the last in a standardization path that has included incubat ... read more