| The Case for Developing Custom Analog SOCs |
December 3, 2012 -- Custom analog SOC (system-on-chip) designs are now a real option for many system houses and OEMs that previously found such designs outside their budgets. The reduction in fabrication costs for older-node processes (especial ... read more |
| 3D ICs with TSVs: Design Challenges and Requirements |
December 3, 2012 -- As demands accelerate for increasing density, higher bandwidths, and lower power, many IC design teams are looking to 3D ICs with through-silicon vias (TSVs). 3D ICs promise "more-than-Moore" integration by packing a great de ... read more |
| Blindsided by a Glitch |
November 19, 2012 -- The blindside blitz. The quarterback's greatest fear. The big hit that arrives with no warning and the cover bypassed. In SOC design, particularly in clock-domain-crossing (CDC) analysis, RTL designers can also believe they ... read more |
| Profiling Defect Sites for Yield Improvement |
November 9, 2012 -- While the industry progressively heads towards IC designs at 20nm and below, the challenges of profitably manufacturing these designs continue to emerge. As foundries confront the issues of manufacturing an acceptable yield, ... read more |
| New IJTAG Standard Simplifies SOC Verification and Test Processes |
November 5, 2012 -- Modern SOCs are a complex mix of embedded-IP cores, customized logic provided by the chip supplier and a myriad of communication interfaces. SOC designers have found that accessing instruments embedded into their chips and em ... read more |
| Solutions for Mixed-Signal SOC Implementation |
October 25, 2012 -- Since virtually all systems-on-chip (SOCs) contain some analog circuitry, many SOC design engineers have some familiarity with mixed-signal implementation. Nevertheless, a new set of challenges is emerging as the amount of an ... read more |
| Vendor-Independent RTL Memory BIST Insertion and Verification |
October 23, 2012 -- ASIC vendors have traditionally incorporated built-in self-test (BIST) and repair solutions in their customers' gate-level netlists. This used to be the common industry practice for technology nodes of 65nm and older. Designe ... read more |
| The IP Blame Game |
October 10, 2012 -- The topic of IP quality in the SOC era is difficult to define, and solutions to problems relating to IP quality, verification, and use are hard to find. Debates rage between IP users, suppliers, and EDA vendors about where th ... read more |
| Already Scanned Today? |
September 21, 2012 -- Since its standardization as IEEE 1149.1 in 1990, JTAG/ Boundary Scan has developed to one of the most important technology within the ensemble of various test strategies. This technology's high dynamics and practical relev ... read more |
| Use the Power of Your SOC to Verify Its Low-Power Design Features |
September 1, 2012 -- The worlds of system-on-chip (SOC) development and low-power design are almost completely intertwined these days. Most SOCs are developed for portable consumer devices where battery life can make or break a product. If the S ... read more |
| Challenges and Requirements for Power-Aware Debugging |
August 27, 2012 -- Traditionally, area and timing have been the major issues faced by IC designers. Now, power has also emerged as a major concern for three reasons. First, low power is favored by numerous end-applications, such as cellular phon ... read more |
| SCE-MI Explained: Macro-based and Function-based |
August 24, 2012 -- SCE-MI stands for Standard Co-Emulation Modeling Interface and is the Accellera standard for bridging two realms: un-timed (HLV, on a host) and timed (HDL, in an emulator). The main goal was to eliminate communication bottlene ... read more |
| Solutions for Mixed-Signal SOC Verification |
August 21, 2012 -- Driven by growth opportunities in mobile communication, networking, power management, automotive, medical, imaging, and security applications, many silicon vendors are refocusing their business on RF, high-performance analog a ... read more |
| Leapfrogging the Competition Through Smart IP Selection |
August 17, 2012 -- The adoption of a reliable design reuse methodology, proliferation of high-quality IP products, and shake-out of the most un-trustworthy IP vendors creates a situation offering a huge potential advantage to system integrators ... read more |
| Hybrid Prototyping Delivers the Best of Both Virtual and FPGA Prototyping to SOC Hardware and Software Teams |
August 3, 2012 -- The complexity and cost of software development is impacting the timely introduction of new electronic system products, often undermining a product's market acceptance due to bugs that hide until after production. Recent indust ... read more |
| 8051s in the Spectrum of Microcontroller Choices |
July 20, 2012 -- There is a broader range of processor choices available to embedded systems and product designers today than ever before. At the higher end, some of the most exciting products use full 32-bit processors, such as the dual-ARM Cor ... read more |
| 3D-IC System Verification Methodology: Solutions and Challenges |
July 20, 2012 -- The performance and cost savings for moving toward through-silicon via (TSV)-based three-dimensional (3D) integration motivations have been identified [1]-[2]. 3D integrated circuit (IC) technology enables shorter critical inter ... read more |
| Testing the 3D Waters |
July 19, 2012 -- There certainly has been no lack of talk these days on the industry's eventual migration to 3D-ICs. No matter which conference you go to or which trade publication you read, you are bound to encounter some 3D-related material. A ... read more |
| The Evolution of Power Format Standards |
July 16, 2012 -- The Silicon Integration Initiative's (Si2's) contribution of the Open Low-Power Methodology (OpenLPM) to the IEEE in 2011 marked an important milestone in the development of power-format standards for the industry. Cadence, amon ... read more |
| Understanding the Low Power Abstraction |
July 6, 2012 -- Electronic systems are inherently complex, and increasingly so with greater integration. What has allowed us to design and verify such systems at all has been the adoption of abstract models that deliberately exclude certain deta ... read more |
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