| Quality and Risk as a Selection Criteria for IP Using VSIA QIP 2.0 |
July 3, 2006 -- When the IP industry emerged in the mid nineties, chip designers had high hopes that reusing highly complex IP would let them close the gap which had opened between the gate capacity of modern process nodes, and the design comple ... read more |
| Evaluate IP Timing Constraints Before Use in SOC Designs |
July 1, 2006 -- When combining intellectual property (IP) blocks from various sources, you must have a complete, high-quality set of timing constraints for efficient SoC timing closure and signoff. Otherwise, IP integration problems can cause lo ... read more |
| Multicore This, Multiprocessor That: It’s all MPSoC |
July 3, 2006 -- There’s lots of chatter about the move to multi-cores on a chip, or multi-processor SoC. At times there appears to be more heat than light on this topic. One designer’s multicore may be what another designer calls multiprocess ... read more |
| Using Dynamic and Static Power Rail Analysis to Maximize Results with Minimum Effort |
June 26, 2006 -- Knowing where and how to apply power rail analysis can save a great deal of time in power planning and verification. Several key concepts can help, beginning with an understanding of appropriate uses for dynamic and static rail ... read more |
| Structuring a Solution |
June 9, 2006 -- Is the digital structured ASIC dead? LSI has pulled the plug. Synplicity is winding down its entire structured ASIC line. Articles appear, almost daily, waxing nostalgic about the rise and fall of an industry. Yet, there is a new ... read more |
| What We Learned About Structured ASICs from RapidChip |
June 9, 2006 -- In recent months, a number of companies have moved away from the structured ASIC business. LSI Logic, Synplicity and Lightspeed have all announced that they will focus on more profitable and faster growing pieces of their busine ... read more |
| Structured ASICs and Platform FPGAs |
June 16, 2006 -- It's a funny old world sometimes. For example, in the back of your mind you might feel pretty sure you know something … and a warm glow of happiness follows you around until you're asked to actually explain it to someone. At tha ... read more |
| The Structured ASIC Debate |
June 16, 2006 -- The debate over the structured ASIC market continues and the fall-out is severe for some suppliers that have invested heavily over the last three years. The big question now is whether the products will continue to survive.
... read more |
| Video Technology Mixes with Structured ASICs |
June 15, 2006 -- Engineers developing video production and video delivery technology have new design options for today’s high-definition systems. There are, of course, ASICs for very high volume applications, but they have long and expensive dev ... read more |
| Structured ASICs and Platform FPGAs: Part 2 |
June 16, 2006 -- In Part 1 of this piece, we first described just what Structured ASICs are, and we then posed the question: "If Structured ASICs are so wonderful, why aren’t more people using them?"
Actually, that really wasn't ver ... read more |
| The Platform Strategy for CE Product Development |
June 14, 2006 -- Ironically, a very mature consumer product sector long ago adopted a design strategy now just being recognized as equally valid for consumer electronics. For decades auto makers’ product lines have shared essentially identical ... read more |
| Seven Habits of Effective Formal Verification Planning |
"Those who fail to plan, plan to fail." This is certainly true when it comes to successful verification, where experience repeatedly demonstrates that success depends on methodical verification planning combined with systematic verification processes.
... read more |
| Combinational Equivalence Checking for Retimed Designs |
June 12, 2006 -- Equivalency checking is an important and necessary step to verify the functional correctness of a design’s implementation. However, circuit retiming introduces changes that strike at the fundamental techniques used by combinatio ... read more |
| Becoming the “Third Force” in FPGAs |
June 9, 2006 -- To become the third major supplier of FPGAs, Lattice developed a product strategy that focused on superiority to Altera and Xilinx in key areas. Our larger competitors often maintain that there is no need in the market for a thi ... read more |
| Critical Area: A Metric for Yield Optimizations in Physical Design |
June 5, 2006 -- While area, timing and power have been the main design objectives for several process generations, the design industry is increasingly focusing on a new goal - yield. Attaining high yield for nanometer designs is a growing challe ... read more |
| Applying Transaction-Level Models for Design and Testbenches |
June 5, 2006 -- Transaction-level modeling (TLM) is an increasingly important tool for both designs and testbenches. Verification involves the comparison of a design implementation with the designer’s intent. As the latter is created at a high l ... read more |
| Transactions for the Masses |
May 22, 2006 -- To handle the increased size and complexity of designs, design and verification methodologies must operate at higher and higher levels of abstraction. These upward shifts in abstraction tend to occur about every decade or so. Tod ... read more |
| Strategies to Prevent IC Failures in Volume Production |
May 18, 2006 -- When IC devices are produced and shipped to customers, it's important that they function as specified in the application environment. A number of strategies and practices can be used to statistically sample and predict how a devi ... read more |
| Networks on Chip for Managing On-Chip Communications |
May 8, 2006 -- Networking has been proven in the computer systems arena to be an extremely effective means of managing communications among any collection of distributed systems that need some level of inter-communications. As more different ty ... read more |
| Survey Shines Light on the State of ESL Design |
May 8, 2006 -- In the world of electronics, new design methodologies are often slow to reach mainstream acceptance. In general, engineers do not adopt new methodologies until design challenges become exceedingly difficult and eventually breaking ... read more |
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