| DFM: What Do the Letters Really Mean? |
July 22, 2005 -- Design for manufacturability (DFM) has become one of the most talked about areas in electronic design automation (EDA). The challenges associated with power, yield, leakage and mask patterning at 90nm process nodes and below hav ... read more |
| Networks on Chip: Challenges and Solutions |
July 20, 2005 -- The network-on-Chip (NoC) design paradigm is viewed as an enabling solution for the integration of an exceedingly high number of computational and storage blocks in a single chip. The practical implementation and adoption of the ... read more |
| RTL Verification without Testbenches |
July 11, 2005 -- Increasingly, designers begin with high-level models to partition and verify system functionality. Best-practicing teams reuse these models within testbenches to verify the resulting RTL designs. However, the cost and brittlenes ... read more |
| Verilog-A/DoE: Simulating Behavioral Models Over Corners |
July 8, 2005 -- Analog circuit modeling has long been a promising avenue of pursuit for circuit/system designers. The idea of obtaining fast, accurate behavioral models of analog circuits is very attractive, especially with increasingly-complex ... read more |
| Improving Test Through Real-Time Information |
July 1, 2005 -- All of us in the semiconductor test business know the issues: cost of test is too high, quality standards are being raised, parts are more complex, storage of excessive test data is overflowing our networks and data warehouses, a ... read more |
| EDA Tools Aim at Improving Yield |
July 1, 2005 -- With each new process node, additional defect mechanisms appear and hinder the ability to achieve desired yield. The trend toward declining yields has created resurgence in the application of design for manufacturing (DFM) method ... read more |
| Advanced Block-Level Bug-Hunting with Assertion-Based Verification Methodology and Hybrid Formal Verification |
June 1, 2005 -- In the past few years, the semiconductor industry has been adding ever larger engineering resources to meet rapidly increasing functional verification challenges. Of particular interest are new verification tools, methodologies a ... read more |
| IP Quality is the Key to Successful SoC Design |
June 6, 2005 -- The growth of IP in silicon chips, both from third parties and internally developed, is a natural response to Moore's Law-shrinking process nodes leading to more complex system-on-a-chip (SoC) designs running at higher clock rate ... read more |
| Software-Configurable Processors on the Rise |
June 1, 2005 -- Ideally, engineers would prefer to base designs on a flexible rather than fixed architecture, such as implementing functionality in software. Software offers flexibility in that new functionality can be introduced over time. Pr ... read more |
| Configurable Processors: What, Why, How? |
June 1, 2005 -- A new type of processor core has been getting a lot of attention lately - a processor you can tailor for a specific application. Configurable processor cores are much faster and can do much more than standard embedded microproces ... read more |
| System Verification for Reconfigurable Processor-Based Systems using SystemC |
June 1, 2005 -- Dynamically reconfigurable processor architectures are likely to find wider acceptance for system design in near future. The key factors driving the adaptation of such systems would be: 1) availability of flexible hardware resour ... read more |
| Formal Verification with ABV Made Practical |
June 1, 2005 -- The complexity of modern SoC designs has created a verification crisis. Engineers cannot imagine all of the possible corner-case behaviors let alone write tests to exercise them. The only way to address the increased complexity i ... read more |
| Boosting Processor Performance with an Optimized Coprocessor |
June 1, 2005 -- Let's address a familiar issue; you need to process more embedded software than the main processor (or processors) can handle, and you have a performance problem. Whether you identified the issue at design planning or discovered ... read more |
| Can Formal Verification Techniques Save Design? |
ASIC/FPGA design is a dying art. This process of creating an ASIC is being replaced by a process of integration. A survey of the state of the art in ASIC design today will produce numerous discussions about how to accelerate the design process by rep ... read more |
| Communications Fabric Leverages Computing Power of FPGA Architectures |
June 1, 2005 -- A wide range of high-performance computing applications are migrating from microprocessors to FPGAs to take advantage of the potentially huge increases in performance, IO bandwidth, size, weight and power. But large and complex a ... read more |
| An EDA Giant's Take on Upcoming Challenges |
June 1, 2005 -- For "DAC month," SOCcentral Contributing Editor Jim Lipman cornered Raul Camposano, Synopsys' Chief Technology Officer and General Manager of the Silicon Engineering Group, to get his opinion on upcoming EDA challenges and ... read more |
| Solving High-Speed Memory Interface Challenges with Low-Cost FPGAs |
May 11, 2005 -- Memory devices are ubiquitous in today's communications systems. As system bandwidths continue to increase into the multi-gigabit range, memory technologies have been optimized for higher density and performance. In turn, memor ... read more |
| Structured ASIC Platforms with Integrated SerDes Cores Offer Performance at Low Cost |
May 6, 2005 -- Structured ASIC platforms have come a long way since their introduction three years ago. Originally conceived as a bridge between design approaches using quick-but- expensive FPGAs or full standard cell ASICs, they have offered us ... read more |
| When Probing Goes in the Chip |
May 2, 2005 -- Today's system-on-chip designs create a situation where system complexity, coupled with time-to-market pressure, make the debug and characterization of these systems more critical and challenging than ever. At the same time the p ... read more |
| The Next Five Years for FPGAs |
May 1, 2005 -- SOCcentral recently had Contributing Editor Jim Lipman sit down with Danny Biran, Altera's recently hired Vice President, Product and Corporate Marketing, to talk about what designers are looking for in FPGAs, structured AS ... read more |
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