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 Category: SOCcentral Feature Articles & Columns: Feature Articles: Thursday, March 26, 2015
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The Future of Configurable Microprocessing 

September 7, 2005 -- Microprocessor cores certainly continue to get their share of attention from both the semiconductor community and those who invest in it. Contributing Editor Jim Lipman sat down with Carl Schlachte, CEO of ARC International ... read more

Structured ASICs: A Risk Management Tool 

September 1, 2005 -- The costs and risks of designing custom silicon are putting innovation out of reach for all but the very bold. Ironically, Moore's Law which forecasts predictable evolution towards finer and finer process geometries makes t ... read more

Standard-Metal: The Ultimate Structured ASIC Fabric 

September 1, 2005 -- According to Dataquest and IBS, structured ASICs will be used for one third of ASIC design starts by 2008 or sooner. This rapid adoption of structured ASICs is driven by the need to reduce overall costs, physical design comp ... read more

Platform ASICs vs. FPGAs  

September 1, 2005 -- Design teams are continually seeking ways of maintaining their competitive edge and improving profitability. The search for solutions that will provide faster time to market, lower cost and higher performance for successive ... read more

Top Five Reasons to Convert Your FPGA-to-ASIC 

September 1, 2005 -- ASIC conversions have been going on for twenty-five years, starting long before there were FPGAs available in the marketplace. ASIC vendors who have focused on conversions through the full twenty-five years and who now offe ... read more

FPGAs and Structured ASICs: A New Reality for ASSP Development  

September 1, 2005 -- Within the next five years, most new ASSP companies will be using FPGAs and structured ASICs to implement their new ideas. The number of new designs utilizing standard cell ASICs will dwindle due to exponential developments ... read more

How Are You Planning to Verify all that DFT? 

August 31, 2005 -- As gate counts continue to swell at a rapid pace, modern systems-on-chip (SoCs) are increasingly integrating more design-for-testability (DFT) capabilities, which already account for as many as 10% of total gates in some ICs. ... read more

Testing an FPGA: When Is Enough, Enough? 

August 22, 2005 -- The world is moving from parallel to serial in order to meet the increasing I/O bandwidth requirements that are now a reality thanks to digital convergence. One has only to explore the new standards that are being deployed, in ... read more

IC-Catalyst: A Technology to Improve Silicon Engineering Productivity 

August 8, 2005 -- The relentless increase in SoC design complexity posed by advanced process technologies is significantly diminishing the reliability of the silicon product. In addition, SoC complexity has made design schedules unpredictable to ... read more

Hybrid Optimization of High Performance Cell-Based Design 

August 4, 2005 -- Automated synthesis-oriented digital integrated circuit (IC) design methodologies have revolutionized the semiconductor industry over the past 25 years. Historically, use of precharacterized and silicon verified "standard cells ... read more

The VSIA and IP Reuse 

August 2, 2005 -- For this month's SOCcentral Executive Interview, Contributing Editor Jim Lipman sat down with Mike Kaskowitz, vice president of the IP division of Mentor Graphics and the president of the VSI Alliance, the open organization dev ... read more

Choosing a Structured/Platform ASIC: Understanding the Market Landscape 

August 1, 2005 -- The rapidly emerging Structured/ Platform ASIC market has a number of companies furiously promoting their competitive offerings. While it can be a challenge evaluating competing products because of the wide variety of new names ... read more

DFM: What Do the Letters Really Mean? 

July 22, 2005 -- Design for manufacturability (DFM) has become one of the most talked about areas in electronic design automation (EDA). The challenges associated with power, yield, leakage and mask patterning at 90nm process nodes and below hav ... read more

Networks on Chip: Challenges and Solutions 

July 20, 2005 -- The network-on-Chip (NoC) design paradigm is viewed as an enabling solution for the integration of an exceedingly high number of computational and storage blocks in a single chip. The practical implementation and adoption of the ... read more

RTL Verification without Testbenches 

July 11, 2005 -- Increasingly, designers begin with high-level models to partition and verify system functionality. Best-practicing teams reuse these models within testbenches to verify the resulting RTL designs. However, the cost and brittlenes ... read more

Verilog-A/DoE: Simulating Behavioral Models Over Corners 

July 8, 2005 -- Analog circuit modeling has long been a promising avenue of pursuit for circuit/system designers. The idea of obtaining fast, accurate behavioral models of analog circuits is very attractive, especially with increasingly-complex ... read more

Improving Test Through Real-Time Information 

July 1, 2005 -- All of us in the semiconductor test business know the issues: cost of test is too high, quality standards are being raised, parts are more complex, storage of excessive test data is overflowing our networks and data warehouses, a ... read more

EDA Tools Aim at Improving Yield 

July 1, 2005 -- With each new process node, additional defect mechanisms appear and hinder the ability to achieve desired yield. The trend toward declining yields has created resurgence in the application of design for manufacturing (DFM) method ... read more

IP Quality is the Key to Successful SoC Design 

June 6, 2005 -- The growth of IP in silicon chips, both from third parties and internally developed, is a natural response to Moore's Law-shrinking process nodes leading to more complex system-on-a-chip (SoC) designs running at higher clock rate ... read more

Advanced Block-Level Bug-Hunting with Assertion-Based Verification Methodology and Hybrid Formal Verification 

June 1, 2005 -- In the past few years, the semiconductor industry has been adding ever larger engineering resources to meet rapidly increasing functional verification challenges. Of particular interest are new verification tools, methodologies a ... read more

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