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 Category: SOCcentral Feature Articles & Columns: Feature Articles: Tuesday, September 02, 2014
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Challenges and Requirements for Power-Aware Debugging 

August 27, 2012 -- Traditionally, area and timing have been the major issues faced by IC designers. Now, power has also emerged as a major concern for three reasons. First, low power is favored by numerous end-applications, such as cellular phon ... read more

SCE-MI Explained: Macro-based and Function-based 

August 24, 2012 -- SCE-MI stands for Standard Co-Emulation Modeling Interface and is the Accellera standard for bridging two realms: un-timed (HLV, on a host) and timed (HDL, in an emulator). The main goal was to eliminate communication bottlene ... read more

Solutions for Mixed-Signal SOC Verification 

August 21, 2012 -- Driven by growth opportunities in mobile communication, networking, power management, automotive, medical, imaging, and security applications, many silicon vendors are refocusing their business on RF, high-performance analog a ... read more

Leapfrogging the Competition Through Smart IP Selection 

August 17, 2012 -- The adoption of a reliable design reuse methodology, proliferation of high-quality IP products, and shake-out of the most un-trustworthy IP vendors creates a situation offering a huge potential advantage to system integrators ... read more

Hybrid Prototyping Delivers the Best of Both Virtual and FPGA Prototyping to SOC Hardware and Software Teams 

August 3, 2012 -- The complexity and cost of software development is impacting the timely introduction of new electronic system products, often undermining a product's market acceptance due to bugs that hide until after production. Recent indust ... read more

8051s in the Spectrum of Microcontroller Choices 

July 20, 2012 -- There is a broader range of processor choices available to embedded systems and product designers today than ever before. At the higher end, some of the most exciting products use full 32-bit processors, such as the dual-ARM Cor ... read more

3D-IC System Verification Methodology: Solutions and Challenges 

July 20, 2012 -- The performance and cost savings for moving toward through-silicon via (TSV)-based three-dimensional (3D) integration motivations have been identified [1]-[2]. 3D integrated circuit (IC) technology enables shorter critical inter ... read more

Testing the 3D Waters 

July 19, 2012 -- There certainly has been no lack of talk these days on the industry's eventual migration to 3D-ICs. No matter which conference you go to or which trade publication you read, you are bound to encounter some 3D-related material. A ... read more

The Evolution of Power Format Standards 

July 16, 2012 -- The Silicon Integration Initiative's (Si2's) contribution of the Open Low-Power Methodology (OpenLPM) to the IEEE in 2011 marked an important milestone in the development of power-format standards for the industry. Cadence, amon ... read more

Understanding the Low Power Abstraction 

July 6, 2012 -- Electronic systems are inherently complex, and increasingly so with greater integration. What has allowed us to design and verify such systems at all has been the adoption of abstract models that deliberately exclude certain deta ... read more

Power Is on Everybody's Mind 

June 29, 2012 -- At the recent Design Automation Conference (DAC) in San Francisco, visitors to the EVE booth learned how system-on-chip (SOC) emulators have evolved to support the needs of modern SOC realization. Recent advances in the hardware ... read more

Test Automation of 3D Integrated Systems 

Advances in packaging technologies have led to the development of three-dimensional (3D) integrated systems that offer the potential to deliver significant improvements in performance, power, functional density, and form factor over systems that rely o ... read more

New Tools Take the Pain out of FPGA Synthesis 

Most FPGA designers are passionate about their work and thrive on the problem-solving and creative aspects of the profession. The job does, however, come with a fair amount of stresses and its share of monotonous tasks. Luckily, EDA companies and FPGA ... read more

The IP Distribution Challenge 

June 15, 2012 -- What comes to mind when you hear the term IP Distribution? How do people like ARM and MIPS get their cores into people's hands? Pricing, contracts and legal issues? Maybe third-party websites like Chip Estimate and Design ... read more

The Design and Verification Challenge for the Decade 

June 14, 2012 -- The real world is analog and computers are digital. These nine words set the stage for the great circuit design challenges of the next decade. To quote G. Dan Hutchenson, president of VLSI Research, "virtual reality is possible ... read more

Low-Power RTL Report 2012 

June 14, 2012 -- This article is based on a report that covers trends in the area of low-power design, based on an independent, global RTL power analysis and optimization survey. By analyzing this comprehensive feedback from design engineers and ... read more

Mixed-Signal Design Trends and Challenges 

June 1, 2012 -- What is mixed-signal design? There may be as many different answers as people asked. Most would agree that mixed-signal is some combination of analog and digital. This article is Chapter 1 from the new book entitled "Mixed-Signal ... read more

Driving A/MS Innovation: An EDA Ecosystem Approach 

June 1, 2012 -- Much of the media focus and discussion within the semiconductor industry is related to mitigating design and manufacturing challenges at nanoscale process nodes. EDA providers continue to develop design tool flows to address thes ... read more

Latest FPGAs Show Big Gains in Floating-Point Performance 

May 16, 2012 -- High-performance computing applications have hit the practical limits of clock speeds for microprocessors. To increase the performance of a computing device, parallelism must be exploited so that more operations can be performed ... read more

An Accurate DRAM Model 

May 14, 2012 -- The Dynamic Random Access (DRAM) memory subsystem is a crucial component of a computing system architecture. The system performance largely relies on efficient memory accesses, and design decisions for the system architecture bas ... read more




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