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 Category: SOCcentral Feature Articles & Columns: Feature Articles: Monday, October 20, 2014
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An Accurate DRAM Model 

May 14, 2012 -- The Dynamic Random Access (DRAM) memory subsystem is a crucial component of a computing system architecture. The system performance largely relies on efficient memory accesses, and design decisions for the system architecture bas ... read more

Augmenting the Transaction Generator with New DRAM and Workload Models 

May 11, 2012 -- Transaction Generator (TG) is a freely available, highly-versatile tool SystemC simulation tool for benchmarking network-on-chips (NoCs). TG is developed at Tampere University of Technology, Finland, in collaboration with other m ... read more

Reaching for the Cloud: What's Next for Interconnects 

April 27, 2012 -- Content — we want it all, and we want it now! At work and at play, we expect our devices to provide easy access to media, games, web sites, email, Facebook, Twitter. We demand that our devices stay connected to the Intern ... read more

Using Formal Technology to Improve Coverage Results 

April 23, 2012 -- Debugging continues to be one of the biggest bottlenecks in today's design flow. Yet, when discussing the topic of debugging among project teams, the first thought that comes to mind for most engineers is related to the ... read more

Resistive RAM: The Future Embedded Non-Volatile Memory? 

April 9, 2012 -- The major drawback to existing embedded reprogrammable non-volatile memory (NVM) solutions, such as EEPROM and Flash, is they add costly processing steps to the standard logic CMOS flow and becomes increasingly incompatible with ... read more

Extending the Metric-Driven Verification Methodology to TLM 

March 30, 2012 -- The electronic design industry has experienced quantum leaps in productivity every time that the abstraction level of design has been raised, as was the case when RTL synthesis enabled verification to move from the gate level u ... read more

Hardware in the Software Sphere of Influence 

March 30, 2012 -- The increasing prevalence of multi-core design and concurrent software execution makes it ever more critical to be able to validate hardware and software processes in concert under system-level scenarios. This level of verifica ... read more

Streamlined Verification Plans Using the Metric Driven Verification Flow 

February 23, 2012 -- A streamlined verification planning processes is required to meet today's quality and productivity expectations. The Metric Driven Verification (MDV) flow introduced by Cadence provides many enablers to achieve these goals. ... read more

Completing Hardware Innovation Cycles in Less than Six Months: An Internet Data Center Server Case Study 

February 1, 2012 -- New market developments and the pressure to leapfrog the competition make it imperative for companies to roll out the next-generation version of their products in record time. Companies that develop ASIC-based systems are ris ... read more

Understanding Formal Verification Concepts-Part 3 

January 31, 2012 -- In this final article in a three-part series about formal verification concepts, we examine the assertion-based verification flow and some of the formal verification algorithms. This kind of approach has become necessary as S ... read more

Understanding Formal Verification Concepts-Part 2 

January 16, 2012 -- In this second article in a three-part series about formal-verification concepts, we examine the assertion-based verification flow and some of the formal-verification algorithms. This kind of approach has become necessary as ... read more

Simulation Coverage and Formal Verification: Unlikely Collaborators? 

January 13, 2012 -- Closing the coverage gap has been a long-standing challenge in simulation-based verification. Formal verification set-up methodologies lack completion measures like coverage on the simulation side. This article articulates a ... read more

Understanding Formal Verification Concepts 

December 9, 2011 -- As complex system-on-chip (SOC) designs grow in size as well as functionality, more and more test vectors must be created and run to get reasonable test coverage. This imposes a cost in the time and effort needed to create th ... read more

Powering the Shift to HLS 

December 6, 2011 -- Low power is now a central concern of digital design, especially for handheld and wireless devices, but also for servers and other computation-intensive applications where the cost of cooling can be quite high. Consequently, ... read more

Handling Clock Synchronization During Power-Driven Synthesis 

October 27,2011 -- Synthesis and layout tools often make design changes in an attempt to introduce power savings. We are aware of a number of incidents where one of these techniques, namely, the insertion of clock gating cells in the clock netwo ... read more

Understanding the Cost of Not Prototyping 

October 24, 2011 -- Before answering the question of the cost of not prototyping let's understand why you should prototype. The prototyping that I am talking about is FPGA prototyping of SOC and ASIC designs before committing the designs to prod ... read more

Breaking the Memory-Performance Bottleneck 

October 17, 2011 -- In recent years, our industry has seen only incremental improvements in memory performance compared to significant improvements in processing performance. The increase in processing performance (via architectural innovations ... read more

A Verification Methodology for 3D-ICs 

October 3, 2011 -- The use of three-dimensional integrated circuit (3D-IC) techniques has been growing in importance because 3D provides a way to increase both data throughput and the amount of functionality on a chip without using more costly l ... read more

Improving At-Speed DFT Coverage Using Early RTL Testability Analysis 

September 20, 2011 -- Delay testing is widely used to check whether a manufactured chip is free of delay defects and meets its performance specification. Common delay testing methods such as logic BIST and at-speed scan testing are applied to in ... read more

Advanced Sign-Off…It's Trending! 

September 13, 2011 -- While much of the discussion at conferences such as DAC are anecdotal, one useful way Real Intent gathers trend data is through our attendee surveys. Hundreds of visitors to the Real Intent booth last June at DAC completed ... read more




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