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 Category: SOCcentral Feature Articles & Columns: Feature Articles: Saturday, October 22, 2016
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Page(s): 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (318 Entries)
New Tools Take the Pain out of FPGA Synthesis 

Most FPGA designers are passionate about their work and thrive on the problem-solving and creative aspects of the profession. The job does, however, come with a fair amount of stresses and its share of monotonous tasks. Luckily, EDA companies and FPGA ... read more

The IP Distribution Challenge 

June 15, 2012 -- What comes to mind when you hear the term IP Distribution? How do people like ARM and MIPS get their cores into people's hands? Pricing, contracts and legal issues? Maybe third-party websites like Chip Estimate and Design ... read more

The Design and Verification Challenge for the Decade 

June 14, 2012 -- The real world is analog and computers are digital. These nine words set the stage for the great circuit design challenges of the next decade. To quote G. Dan Hutchenson, president of VLSI Research, "virtual reality is possible ... read more

Low-Power RTL Report 2012 

June 14, 2012 -- This article is based on a report that covers trends in the area of low-power design, based on an independent, global RTL power analysis and optimization survey. By analyzing this comprehensive feedback from design engineers and ... read more

Mixed-Signal Design Trends and Challenges 

June 1, 2012 -- What is mixed-signal design? There may be as many different answers as people asked. Most would agree that mixed-signal is some combination of analog and digital. This article is Chapter 1 from the new book entitled "Mixed-Signal ... read more

Driving A/MS Innovation: An EDA Ecosystem Approach 

June 1, 2012 -- Much of the media focus and discussion within the semiconductor industry is related to mitigating design and manufacturing challenges at nanoscale process nodes. EDA providers continue to develop design tool flows to address thes ... read more

Latest FPGAs Show Big Gains in Floating-Point Performance 

May 16, 2012 -- High-performance computing applications have hit the practical limits of clock speeds for microprocessors. To increase the performance of a computing device, parallelism must be exploited so that more operations can be performed ... read more

An Accurate DRAM Model 

May 14, 2012 -- The Dynamic Random Access (DRAM) memory subsystem is a crucial component of a computing system architecture. The system performance largely relies on efficient memory accesses, and design decisions for the system architecture bas ... read more

Augmenting the Transaction Generator with New DRAM and Workload Models 

May 11, 2012 -- Transaction Generator (TG) is a freely available, highly-versatile tool SystemC simulation tool for benchmarking network-on-chips (NoCs). TG is developed at Tampere University of Technology, Finland, in collaboration with other m ... read more

Reaching for the Cloud: What's Next for Interconnects 

April 27, 2012 -- Content — we want it all, and we want it now! At work and at play, we expect our devices to provide easy access to media, games, web sites, email, Facebook, Twitter. We demand that our devices stay connected to the Intern ... read more

Using Formal Technology to Improve Coverage Results 

April 23, 2012 -- Debugging continues to be one of the biggest bottlenecks in today's design flow. Yet, when discussing the topic of debugging among project teams, the first thought that comes to mind for most engineers is related to the ... read more

Resistive RAM: The Future Embedded Non-Volatile Memory? 

April 9, 2012 -- The major drawback to existing embedded reprogrammable non-volatile memory (NVM) solutions, such as EEPROM and Flash, is they add costly processing steps to the standard logic CMOS flow and becomes increasingly incompatible with ... read more

Hardware in the Software Sphere of Influence 

March 30, 2012 -- The increasing prevalence of multi-core design and concurrent software execution makes it ever more critical to be able to validate hardware and software processes in concert under system-level scenarios. This level of verifica ... read more

Extending the Metric-Driven Verification Methodology to TLM 

March 30, 2012 -- The electronic design industry has experienced quantum leaps in productivity every time that the abstraction level of design has been raised, as was the case when RTL synthesis enabled verification to move from the gate level u ... read more

Streamlined Verification Plans Using the Metric Driven Verification Flow 

February 23, 2012 -- A streamlined verification planning processes is required to meet today's quality and productivity expectations. The Metric Driven Verification (MDV) flow introduced by Cadence provides many enablers to achieve these goals. ... read more

Completing Hardware Innovation Cycles in Less than Six Months: An Internet Data Center Server Case Study 

February 1, 2012 -- New market developments and the pressure to leapfrog the competition make it imperative for companies to roll out the next-generation version of their products in record time. Companies that develop ASIC-based systems are ris ... read more

Understanding Formal Verification Concepts-Part 3 

January 31, 2012 -- In this final article in a three-part series about formal verification concepts, we examine the assertion-based verification flow and some of the formal verification algorithms. This kind of approach has become necessary as S ... read more

Understanding Formal Verification Concepts-Part 2 

January 16, 2012 -- In this second article in a three-part series about formal-verification concepts, we examine the assertion-based verification flow and some of the formal-verification algorithms. This kind of approach has become necessary as ... read more

Simulation Coverage and Formal Verification: Unlikely Collaborators? 

January 13, 2012 -- Closing the coverage gap has been a long-standing challenge in simulation-based verification. Formal verification set-up methodologies lack completion measures like coverage on the simulation side. This article articulates a ... read more

Understanding Formal Verification Concepts 

December 9, 2011 -- As complex system-on-chip (SOC) designs grow in size as well as functionality, more and more test vectors must be created and run to get reasonable test coverage. This imposes a cost in the time and effort needed to create th ... read more

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