| Breaking the Memory-Performance Bottleneck |
October 17, 2011 -- In recent years, our industry has seen only incremental improvements in memory performance compared to significant improvements in processing performance. The increase in processing performance (via architectural innovations ... read more |
| A Verification Methodology for 3D-ICs |
October 3, 2011 -- The use of three-dimensional integrated circuit (3D-IC) techniques has been growing in importance because 3D provides a way to increase both data throughput and the amount of functionality on a chip without using more costly l ... read more |
| Improving At-Speed DFT Coverage Using Early RTL Testability Analysis |
September 20, 2011 -- Delay testing is widely used to check whether a manufactured chip is free of delay defects and meets its performance specification. Common delay testing methods such as logic BIST and at-speed scan testing are applied to in ... read more |
| Advanced Sign-Off…It's Trending! |
September 13, 2011 -- While much of the discussion at conferences such as DAC are anecdotal, one useful way Real Intent gathers trend data is through our attendee surveys. Hundreds of visitors to the Real Intent booth last June at DAC completed ... read more |
| FPGA Design: From Top-Down to Bottom-Up |
June 2, 2011 -- Implementing an FPGA design used to be straightforward. It was almost as simple as pressing the big RUN button on your synthesis tool followed by automated place and route. Out popped an initial incarnation of your design. ... read more |
| Clarifying Language/Methodology Confusion in FPGA Design |
June 1, 2011 -- In the times of a not so rosy economy and constantly growing design sizes, FPGA designers are constantly facing surprises: old companies go away, taking tools and languages with them, new languages and methodologies appear. The o ... read more |
| Adopting a Flexible FPGA Verification Methodology |
June 1, 2011 -- As system-on-chip (SOC) designs continue to increase in size and complexity, the verification task becomes the bottleneck that can take up to 70% of the overall SOC development effort. As a result, any method that can help to red ... read more |
| A Third Way in FPGA Development |
June 1, 2011 -- At first, the claim that FPGA tools and methodologies can impose standardization on everything from design creation to sign-off seems sound. Given the competition among vendors and the relative maturity of the electronic design a ... read more |
| Is Your CDC Tool of Sign-Off Quality? |
May 13, 2011 -- First-generation tools historically evolved as extensions of simple linters and source checkers or by the application of basic formal engines in an attempt to solve the CDC problem. These tools generated voluminous reports and re ... read more |
| Using Cost-Effective and Secure Field-Programmable 1T-OTP to Emulate MTP |
April 28, 2011 -- Applications for non-volatile memory (NVM) encompass a wide range of programming requirements. Some products require one-time programmable (OTP) memory that is programmed during chip fabrication; mask ROM is good for this purpo ... read more |
| Planning Formal Verification Closure |
April 20, 2011 -- Although simulation-based coverage closure processes are generally well understood (yet hard to achieve) the process for achieving formal property checking proof closure is not well understood. In certain cases, the engineer is ... read more |
| IP Gets Smarter |
April 1, 2011 -- We are seeing an increase in technological innovation at phenomenal rates, despite any economic aftermath. Of course, this brings new (and sometimes near impossible) design requirements for our "smart" devices. This chain react ... read more |
| Factors Compelling Greater Use of Embedded One-Time Programmable Memory |
March 24, 2011 -- The need to provide more functionality at lower cost in small portable devices is driving the demand for more processors on a single chip. Market research firm In-Stat cites MCUs, DSPs, applications processors, and baseband pro ... read more |
| Thru-Silicon Vias: Current State of the Technology |
February 25, 2011 -- Thru-silicon vias (TSVs) have become a very hot topic in in recent months. Ever since Xilinx reported that it is using a 2.5D TSV approach for its Virtex-7 FPGAs, the industry started to salivate with the prospects of this n ... read more |
| Boost Verification Quality with Intelligent Testbench Automation |
February 23, 2011 -- No matter the industry, the introduction of automation technology always tends to produce angst. Think of the story of American folk hero John Henry who raced against a steam-powered hammer and won, only to drop dead with th ... read more |
| Mind the Design and Verification Gap |
February 16, 2011 -- Would you ever use a wrench to tighten a Philips screw? Or hammer a square peg into a round hole? Chip design today has become more of verification task than design. Designers spend more than 50% of their time trying to come ... read more |
| Using Formal Verification to Control X Propagation |
January 19, 2011 -- Adding X states to represent unknown values can provide significant benefits in RTL verification, but runaway X propagation during simulation can hide multiple bugs that are likely to show up in silicon. Current Verilog simul ... read more |
| The Need for a Comprehensive SOC Test Platform |
January 17, 2011 -- Silicon test is the final arbiter that determines if an integrated circuit should be packaged and ultimately shipped to a customer or is defective and should be scrapped. Consequently, a poor test strategy and methodology can ... read more |
| Do You Have the Next-Generation Verification Flow? |
January 13, 2011 -- I have been involved in verification projects for the last ten years. One thing I can say for sure is that the level of complexity is ever rising for both design and verification. With more and more ASICs being designed with ... read more |
| Is CDC (Clock Domain Crossing) Analysis a Misnomer? |
January 10, 2011 -- The high-tech industry is chock-full of acronyms. Each time a new problem is identified, out comes a new acronym that quickly gets standardized. It is very typical for complex new problems in, for example, our VLSI design ind ... read more |
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