July 24,2006 -- Give me strength! I'm too young to handle all of this excitement. As I pen these words, DAC 2006 is almost upon us (in fact, as I'm writing this, I'm at 30,000 feet flying out to San Francisco to join the throng and see all that there is to be seen). As is usual at this time of the year, the "Big Boys" in EDA have their PR battalions fully mobilized with press releases plummeting out of the skies and exploding all around us. The problem is that, with this barrage of publicity assaulting us from all sides, it's easy to miss some of the noteworthy things that are happening in the wings.

As verification expert Brian Bailey once told me: "When it comes to innovation in the EDA field, there is only one place to look: the small startup companies. While some established EDA companies have managed to come up with one or two new tools, most of the creativity comes from the startups."

For this reason, last year my pre-DAC 2005 "Cool Beans" column was entitled "Don't Forget the Little Guys." This turned out to be rather popular. So much so, in fact, that I started receiving emails a few months ago saying: "Are you going to be doing a 'Little Guys' column again this year?" But of course we are, and here it is! As before, just for giggles and grins, we'll introduce them in reverse alphabetical order (because otherwise poor old Xoomsys always comes out last).

Xoomsys, Inc., Booth #1624

How time flies. Founded in 2003, Xoomsys is a relative newcomer to the EDA industry ( in fact, this is only their second year at DAC). Today's nanometer designs require increasing amounts of analog simulation at the transistor level for the detailed analysis of structures such as clock trees, for example. This analysis often demands full SPICE-level accuracy, but it simply isn't possible to handle the computational requirements of simulating a large microprocessor's clock tree using conventional SPICE on a single processor. Zoomsys has the technology to analyze your existing SPICE-level netlist, partition it, and then distribute the simulation across multiple computers and simulators (it uses your existing SPICE simulators licenses).

ViASIC, Booth #1108

I understand that we can expect to see a lot going on at the ViASIC booth this year. As you may recall, they have developed two "standard metal" Structured ASIC fabrics; one requires the customization of only a single via layer, while the other (whose underlying logic is based on standard cells) requires the customization of only two metal layers. Of particular interest is the fact that one of ViASIC's customers - Triad Semiconductor - will be presenting their latest-and-greatest via-configurable mixed signal array products, which are based on ViASIC's underlying technology.

Verific Design Automation, Booth #3345

On the basis that Verific's CEO and COO both measure in at 6'5" (six feet five inches), it seems a little strange to be calling them "The Little Guys". This is especially true on the basis that - even though the Verific folks have only a 10' x 20' booth at this year's DAC - their presence is felt throughout the show. This is because they build Verilog, SystemVerilog, and VHDL front-ends for EDA applications, and many tools from other EDA companies use Verific's parsers and elaborators. At this year's DAC, Verific will showcase its implementation of the IEEE 1800 (SystemVerilog) standard. This puts them ahead of the game, because a lot of companies are discovering how difficult it is to build this on their own. Not a bad position to be in for a company with only 10 people on the payroll.

Solido Design Automation, Booth #3012

Formed in 2005 and currently boasting 12 employees, Solido Design Automation is a newcomer on the EDA block. Just a few weeks ago (June 26, 2006) the folks at Solido announced that they had raised 2.5 million in funding and that they are pioneering a transistor-level design enhancement tool suite that will address emerging challenges for analog/mixed-signal, custom digital, and memory designers. Solido will be giving private demo's at their booth, so why not drop around and see what they have brewing?

Rio Design Automation, Booth #3155

As you've no doubt heard, the folks at Rio have developed a tool called RioMagic that sits directly between existing chip design and package design tools and works on the chip and the package designs concurrently. For example, RioMagic concurrently performs I/O placement and bump assignment on the chip - and escape analysis and escape routing on the package. The result from the chip side of the fence is optimal die size and optimal bump pitch and optimal bump assignment to match the package. The result from the package side of the fence is to use the cheapest package with the smallest number of layers and to make all of the assignments in such a way as to minimize any power integrity and signal integrity issues. At this year's DAC, Rio is announcing that RioMagic now includes full support for wire bond and flip chip designs.

Pulsic, Booth #3073

Claiming to lead the field with regard to shape-based physical design solutions, Pulsic provides advanced tools for complex analog, custom digital, and mixed-signal IC and system-on-chip (SoC) designs. At this year's DAC they will be announcing an integrated design environment called Unity, which is targeted at the high-volume IC market. Unity is a single system comprising floorplanning, placement, routing, editing, signal integrity, and timing applications. They will be exhibiting the Unity platform at their booth, with customer shipments to follow later this year.

ProDesign, Booth # 3020

Founded in 1981, the initial idea behind Pro Design was to support the electronics industry with tools and services. One example of their wares is CHIPit, which they describe as: "A verification and validation system that supports developers throughout the entire project lifecycle, enabling them to check both hardware and software and adapt them to the state-of-the-art." With around 85 employees, ProDesign is starting to be a "Medium-sized Guy." In fact, in June of this year, Pro Design was awarded the "Top 100" quality seal, which is conferred every year as part of a nationwide comparative study of small and mid-sized German companies (Pro Design also placed fifth in the "innovative success" category.)

Poseidon Design Systems, Booth #3355

As you may recall, once you've created a C program, you can use Poseidon's Triton Tuner application to perform a performance analysis of the complete application running on a target architecture, thereby identifying those portions of C code that will benefit from acceleration. Next, the Triton Builder utility automatically partitions the system into the portions that will remain as software running on the processor and those that are to be synthesized into computes. In addition to synthesizing the compute cores, it also creates all of the logic and software necessary to connect these cores back into the complete application. At this year's DAC, they are going to be showcasing some improvements in their synthesis technology, the ability to integrate into high performance memory controllers, support for new processors and implementation fabrics, and full support for VHDL.

Ponte Solutions, Booth #2204

OK, what do the folks at Ponte do? Put your hands up if you know . . . Hmmm, I don't see many hands out there. In fact, this is a rather interesting company in Design-for-Manufacturability (DFM) space, not the least that the entire management team is Armenian (apart from one guy who slipped in while no one was looking) and they have a development center in Armenia. They are also unusual in that they didn't actually announce their first product until it was in its second revision. Now, just one year after their official launch, Ponte is integral to both the Chartered and TSMC DFM initiatives and they have a revenue stream (for which I envy them). At this year's DAC, the folks at Ponte will be showcasing a yield sensitivity analysis system for nanometer designs.

OASIS Tooling, Booth #3051

As we should all know by now, OASIS is the new data format that will (eventually) replace GDSII. For the last two years, the guys and gals at OASIS Tooling have been working with the leading developers and users of OASIS. Exhibiting at DAC for the first time, the company will demonstrate the broader capabilities of OASIS, including advanced OASIS infrastructure, applications, verification, functionality, and OASIS acceleration hardware. Of particular interest is the fact that they will be populating their booth with grad students from Berkeley that have been using the OASIS standard and capabilities. They are also hoping to … but no, I'm sworn to silence; you'll just have to visit their booth to discover more.

Manhattan Routing, Booth #3349

The chaps and chappesses at New Your City-based Manhattan Routing focus their efforts on post-route analysis and optimization. They boast that their Physical Window and Optimization Cockpit technology - which has been used on designs all the way down to the 65nm technology node - allows multi-mode/multi-corner analysis and optimization to close the "last 100 paths" violating timing. In turn, this allows users to efficiently and predictably close timing on design and tape-out at better performance and in shorter time than if using standard place-and-route tools on their own. The folks at Manhattan say that their tool's high-capacity, high-performance database allows full chip designs comprising tens of millions of gates to be effectively timing closed.

Lynguent, Booth #2214

This company is another new-kid-on-the-block in the analog/mixed-signal (AMS) arena. As part of their recent launch, Lynguent announced its first product, ModLyng, which allows engineers to create, maintain, debug, and translate AMS models faster than ever before. In the case of existing models, ModLyng imports the model code, it automatically creates a topological view of the model, and it interprets the electrical equations and statements in the body of the model. Engineers can augment and extend their models with new equations and pre-configured behaviors. Alternatively, engineers can use ModLyng to develop new models, such as behavioral model blocks for speeding design simulation and validation. All models may be exported to the same language in which they were written, or they can be automatically translated into another language.

Kimotion, Booth #2302

There are several good reasons to integrate analog and digital functions on the same chip; combining the two can be cheaper, smaller, and consume less power. Sounds easy, but it isn't. Analog circuits are typically hand-crafted and very sensitive to the environment in which they are used. When you try to put them on the newest process available from the fab - and when you need to locate them next to some busy digital circuitry - you're asking for trouble. Enter the folks at Kimotion, who provide software that leverages the analog designers' expertise in the form of testbenches they prepared when they first build their circuits. Kimotion uses this groundwork to automatically analyze, verify, and optimize a circuit's performance across environment and statistical process variations, and also to automatically generate models that can be used to speed up these tasks.

Gradient Design Automation, Booth #2328

The folks at Gradient specialize in full-chip thermal analysis for digital and mixed-signal ICs. Their initial software product, FireBolt, provides detailed 3D temperature analysis directly within the digital IC design flow. FireBolt can help engineers improve their leakage power (which is highly sensitive to transistor temperature), improve the accuracy of their reliability calculations, and reduce wasteful guard-banding against on-chip variations. Just a couple of month's ago in Aprin 2006, Gradient launched its second product, CircuitFire. This little scamp focuses on the thermal analysis or analog and mixed-signal ICs. Working at the transistor level, it can quickly and accurately analyze the steady-state temperature of the IC. CircuitFire can then output temperature per instance, which - in turn - can be annotated directly into the circuit simulation. This gives designers the ability to predict - prior to tape-out - the true impact of temperature on their circuits' behavior and to avoid re-spins due to thermal problems.

EVE, Booth #924

Founded at the start of the new millennium in 2000, advanced verification specialist EVE is an inventive EDA startup that continues to defy everyone's expectations. Earlier this year, it closed its fiscal year 2006 with strong bookings growth of 40% over the previous year (if only we could all say this about our respective companies). The reason the folks at EVE are doing so well is their ZeBu (short for "Zero Bugs"), which is claimed to combine the best aspects of traditional emulation and rapid prototyping systems into a single, unified environment for ASIC and SoC debugging, and embedded software validation. Boasting a top speed of 200 MHz, ZeBu addresses hardware-software integration and embedded software validation on large designs (some exceeding 10-million logic gates). Its fully automated compiler, testbench acceleration, and interactive design debugging capabilities make this little rapscallion a formidable alternative to internally developed FPGA prototypes.

Celoxica, Booth #3951

As a company, Celoxica has been going through something of a transformation in the past couple of years. They are no longer a pure EDA company providing only design tools, because they have also donned the role of system creator for commercial products. At this year's DAC, Celoxica will be demonstrating why their Agility Compiler has become the tool of choice for behavioral design and synthesis for SystemC. Providing a single solution for FPGA design and ASIC/SoC prototyping, Celoxica's tools have been used in multiple high-visibility design successes, including leading hybrid engines, "bomb-sniffing" technologies, and video/image-processing applications. At this year's DAC, Celoxica will also be demonstrating new hardware and software breakthroughs in accelerated computational engines bringing supercomputing power to cost-effective commercial applications.

Calypto Design Systems, Booth #628

Bluespec, Booth #4163

There's a lot of interest in behavioral synthesis at the moment, most of which is focused on synthesizing C/C++/SystemC/etc. representations into RTL (or directly into gates). Well, the folks at Bluespec come at things from a somewhat different angle. Using SystemVerilog as a base, they've augmented this little scamp with their own extensions to raise it to a higher level of abstraction. The result is a behavioral synthesis solution that fully addresses general-purpose control structures and complex datapaths. The folks at Bluespec claim that their tools allows ASIC and FPGA designers to significantly reduce design time (over a 50% reduction in time to verified netlist), and reduce the bugs and re-spins (less than half of the bugs compared to traditional RTL design) that contribute to product delays and escalating costs. Recently, they announced support for SystemC, and they are bouncing round with excitement at the possibility of demonstrating everything to you at this year's DAC.

Brion Technologies, Booth #3062

The features (structures) on the silicon chip are now smaller than the wavelength of the light used to create them, which causes lots of problems. Thus, the manufacturing folks run a variety of resolution enhancement techniques (RET), such as optical proximity correction (OPC), which modifies the GDSII files by augmenting existing features or adding new features. A few years ago, the folks at Brion entered the market with a mega-cool, extremely fast, highly-accurate, rule-based OPC verification solution. Sometime later, they started performing the OPC step itself. Now, they have some really exciting news, because the weird and wonderful effects we're seeing at the 65 nm technology node mean that it's becoming necessary to account for lithographic effects earlier in the design process. Thus, Brion and Magma recently announced that they are working together to introducing accurate lithographic simulation into the physical design team's engines. Feel free to meander by the Brion and Magma booth's to ask for more information.

Berkeley Design Automation, Booth #1924

Earlier in this decade (circa 2002), only around 1 in 5 chips had a significant amount of analog/RF content. By comparison, these days approximately 4 out of 5 chips have enough analog/RF content to make a grown man cry. Furthermore, analog considerations are becoming pervasive with today's process technologies, even in the most digital of chips. Enter the folks at BDA, which was founded in 2003 and currently boasts around 20 employees. BDA is focused on removing the analog/RF analysis gap; that is, the difference between what designers can observe using traditional simulators versus the behavior of the actual silicon. The engineers at BDA have developed a set of powerful new circuit analysis techniques for the precise and fast analysis of analog and RF ICs. In their private suite at this year's DAC, they'll be describing how to use their technology to solve the toughest analog/RF IC verification problems.

Azuro, Booth #1928

The clock tree and associated registers in a modern digital IC can consume up to 80 percent of the chip's dynamic power. Enter the folks at Azuro. Using their technology, you don't need to add any clock-gating statements into your RTL. Instead, you use ideal clocks all the way through physical synthesis and placement. Then, just before final routing, you run Azuro's tools, which use standard file formats as inputs (Verilog netlists, DEF and PDEF files for placement, .lib and LEF library files for other data, and so forth). Featuring an innovative vector-less approach to average-case power estimation, these tools perform intelligent clock tree synthesis, which simultaneously inserts and optimizes clock gating and buffers. As the folks at Azuro once told me, "There's a lot more juice to come out of the clock-tree orange, and our tools take that orange and squeeze it until its pips squeak!" At this year's DAC, Azuro will be highlighting the latest version of their technology targeted at 65nm designs, including features to support variability aware power reduction as well as support for designs with multiple voltage islands.

Avantest Technology Solutions,

Last but certainly not least, we have the folks from Advantest, who will be demonstrating their new CertiMAX product (they can't have named it after me, can they? Wait until I tell my mom!). CertiMAX is said to: "Enable 'real world' event-based semiconductor validation using a PXI-based environment without imposing any of the traditional limitations of cycle-based test." Well, that certainly sounds good (I wonder what it means?). Furthermore, CertiMAX is claimed to: "Revolutionize the validation environment by allowing the functional verification, debug, and characterization of first silicon without deviating from the design environment." And who amongst us would say that this wasn't a good thing? Hmmm, I was going to say that we should all go to their booth and ask for a demo, but I'm not sure if they're actually attending DAC this year (if they are, I'll track them down).

Did somebody say "Cool Beans"?