May 23, 2007 -- I can't believe it! It's that time of the year again! The 44th Design Automation Conference (DAC 2007) is almost upon us! As we all know, this is the time when the "big boys" of EDA really start to mobilize their PR and marketing battalions. In my mind's eye, I can visualize these bronzed and oiled troops (sorry, I'm projecting again) having trained furiously in top secret camps for the last few months. Now, at their peak of physical fitness and endurance, their skills are honed to perfection and they're poised for the fray.
Meanwhile, their head-of-department generals (who've been undergoing their own intensive preparations over cocktails in luxury beach resorts around the world) are ready to launch an all-out barrage* of press releases and product announcements.
* You learn something new every day — or, at least, I do. In the preceding paragraph I was, of course, using the word "barrage" in its military sense meaning "a heavy barrier of artillery fire". However, I just discovered that this word also has a mycological meaning, where mycology — as you are no doubt aware — is the branch of biology dealing with fungi. In this context, it appears that "barrage" refers to "an aversion response of sexually incompatible fungus cultures that are growing in proximity, revealed by a persistent growth gap between them." Well, who would have "thunk"? But we digress.
As I pen these words I can imagine the final "cannon" sequence from Tchaikovsky's 1812 Overture: "Dum-dum-dum dum-dum-dum-dum dum-dum-dum-dum dum-duummm BOOM, dum-dum-dum dum-dum-dum-dum dum-dum-dum-dum dum-duummm BOOM. . ."
And, with each BOOM, another bombardment of press releases commences. You can run, but you can't hide. Meanwhile, the folks at the smaller EDA (and related) companies are jumping up and down waving their hands in the air crying: "Don’t forget about us!" Of course we won't! That's why we have this annual "Don’t Forget the Little Guys!" column!
Sad to relate, however, I personally won’t be going to DAC this year. The DAC committee took me by surprise by having it so early (it usually occurs around the middle of the month). The problem is that I'm celebrating the 30th anniversary of my 20th birthday, and I already have a big party planned with my family and friends. So the following list reflects some of the companies that I would be going to see if I were to be at DAC. But since it's fallen to me to party by the pool eating gourmet food and quaffing** exotic drinks, you'll have to go and see them for me and then e-mail me to tell me what you think. (**Quaffing is similar to regular drinking, except that you tend to spill more down the front of your chest.)
We'll cover these companies in reverse order (otherwise poor old Xoomsys always ends up at the tail-end of the queue).
Xoomsys (Booth # 7178)
The guys and gals at Xoomsys are developing a scalable, distributed processing solution for accurate large-scale circuit simulation using a combination of industry-standard circuit simulators and inexpensive Linux computing clusters with their "secret sauce." Now we know this must be good stuff, because Raul Camposano was so excited that he recently gave up his position of CTO at Synospsy (a position most of us would give our wife's life savings to hold) to become CEO of Xoomsys.
Founded in 1999, Verific may well have the tallest management team in EDA, because both CEO (Rob Dekker) and COO (Michiel Ligthart) are well over 6ft in height. Verific is quietly, though effectively, serving as the front-end design team for about 15% of all the DAC exhibitors.
Applications vary, from synthesis, emulation, and prototyping; to formal verification and power and signal integrity; to design entry and embedded software development. Each of these companies has integrated Verific’s HDL Component Software (C++ source code-based SystemVerilog, Verilog, and VHDL parsers, analyzers and elaborators).
Synfora (Booth # 3275)
Most consumer devices – cameras, phones, TV’s – have reached a new complexity plateau (7MP, 3G, HD) and are now looking at the next step up to entice us to buy the "next new thing." The problem with this complexity is that projects are slipping and missing market windows.
But fear not, because the chaps and chappesses at Synfora say that their technology has demonstrated the ability to let junior engineers create complex functionality with the same results as an experienced engineer in a fraction of the time. To quote one customer, “Making algorithm creation the critical path item is a beautiful thing!”
Those little scamps at Solido are developing transistor-level statistical design and verification tools for analog/ mixed-signal, custom digital, and memory designers.
This transistor-level statistical design and verification technology provides statistical sampling, trade-off analysis, circuit characterization, and circuit enhancement to discover problems and help designers explore opportunities to compensate for those problems. In turn, designs are better able to withstand process variations and meet specifications without being over-designed.
The folks at SoftJin provide customized EDA tools using a combination of EDA building blocks and custom tool development services. From a humble start in 2001, SoftJin has now grown to a team of 90 engineers based in Bangalore, India.
SoftJin offers EDA "building blocks" that can be licensed by in-house CAD groups in semiconductor companies to develop their own tools, which can then be used royalty free. Thus, the customer gets a customized solution that can be used company-wide without paying for each additional seat.
The little rapscallions at Silicon Navigator provide an open programmable framework, engines, services, and products for digital and custom design that facilitate the creation of new chip design environments at half the cost and a fraction of the time.
Since 2004, they have been developing and delivering OpenAccess-based plug-in solutions. This enables custom solutions to be assembled as component software, allowing CAD departments to augment their existing solutions by providing new highly productive development environments for their internal customers.
Power consumption is now at the forefront of ASIC and system-on-chip (SOC) development concerns. To address this, the guys and gals at Sequence focus on delivering software solutions for power management and low-power design closure that provide designers with a competitive advantage in aggressive nanometer design technology markets.
Sequence's design-for-power (DFP) flow, attacks the challenges of low-power design holistically, from RTL to GDS. The word on the street is that customers already employing Sequence’s DFP Flow are reporting RTL power reductions of up to 50%, a 50% speed-up in design closure times, and leakage power reduction of up to 1,000X.
Founded in 2003, the little ragamuffins at Rio have been furiously developing package-aware chip design software. Using their RioMagic, chip designers can make optimal trade-offs between the chip layout, wires within the chip package, and PCB connections, thereby ensuring that the chip fits the electronic system.
Suffice it to say that Cadence and Magma are believers, because both have invested in Rio. In fact, the folks at Magma have enhanced their flip-chip design support through the integration of their Talus Vortex and Blast Fusion physical design systems with Rio’s RioMagic.
Real Intent is a privately held EDA company whose mission is to improve logic verification efficiency for its customers. This verification ranges from CDC (clock domain crossing) to exception verification and static functional verification.
At DAC 2007, the folks at Real Intent will be announcing EnVision TCV, which they consider to be the first true timing closure verification tool in the market. Apparently, EnVision TCV fills holes in static timing and functional verification that can cause chip delays and project delays.
Founded in 1981 by Helmut Mahr, privately held ProDesign has just 80 employees around the world, but they've certainly made an impression, especially in the European EDA community.
The company's CHIPit product line of verification platforms provides verification and validation throughout the SOC and ASIC project life cycle. Meanwhile, IMAGEit products, based on FPGA technology, offer tremendous processing capabilities in the field of high-speed image processing. Last but not least, the guys and gals at ProDesign offer a full range of electronics manufacturing services from conception, through development and production, to the fully tested product, including CPLD, FPGA, and ASIC designs, microcontroller-based designs, and printed circuit board layout.
The little scamps at Ponte Solutions develop and market unique model-based software products and design for manufacturing (DFM) solutions that analyze, predict, and reduce the impact of process variability during the manufacture and design of semiconductors.
A leader in DFM critical area analysis, Ponte translates physical, chemical, and layer-based manufacturing process variability into deviations from original design intent in a form that makes sense to the design engineers.
The guys and gals at Optimal spend all their waking hours developing a unified analysis environment for 3D signal, power and thermal integrity (they know how to have a good time).
Optimal’s ability to co-analyze the chip, package and PCB for power, signal, and thermal integrity is of great value to design teams. Optimal can model RDL+package+PCB, and the resulting model can then be used by IC analysis tools as real-world boundary conditions.
Today's SOCs typically include large amounts of memory. Furthermore, designers typically need to use a variety of different memory types. The problem is that many memory IP providers supply only a limited number of types.
Enter the chaps and chappesses at Novelics, who have a mega-cool web-based memory compiler called MemQuest that lets you specify the width and depth of the memory block you require along with the type of memory, such as their coolSRAM-1T (one transistor), coolSRAM-6T (six transistor), coolOTP (one-time programmable), coolREG (register file), coolROM (read-only memory), and coolCACHE (cache memory for processor cores). Why are these all prefixed with the word "cool"? Well, these memories are claimed to use half the power of other typical solutions while — at the same time — occupying half the area and providing twice the performance!
Those cunning little rapscallions at Lynguent produce and supply integrated analog/ mixed signal (AMS) design development products that enable designers in the global semiconductor and electronics industries to create, maintain, re-use, debug and validate AMS models and related technology (try saying that three times quickly).
Lynguent is tackling a problem that has persisted since the dawn of electronics — how to raise the productivity of analog engineering teams. Its technology is unique at this point and will probably remain so for at least another year. It is the only company focused on driving a significant acceleration of the AMS model development and validation processes.
The folks at Lightspeed Logic provide mask-reconfigurable Structured ASIC intellectual property (IP) to IDM and fabless semiconductor manufacturers worldwide. As opposed to a fabric based on proprietary cells (logic functions), Lightspeed's technology is based on cells from the foundrys' standard libraries. Using these library cells lets Lightspeed dramatically increase the availability of its offering (and reduce risk) by leverage all of the work performed by the fab in qualifying the new process.
Lightspeed's customers, which include some of the world’s largest IDMs in both Europe and North America, are using its IP to build high volume ASSP, CSSP, and SOC devices at the 130-, 90-, 65-, and 45-nm process nodes.
How are you planning to verify your mixed-signal circuits? If you are going to verify a mixed-circuit design using trial and error methods — or expensive Monte Carlo runs — then the guys and gals at Kimotion say they can offers a more efficient and comprehensive solution.
Although Kimotion is a start-up, they claim that they are going to revolutionize mixed-signal verification. In a nutshell they have tools that allow circuit and system designers of analog and mixed-signal integrated circuits to build performance models that enable much more thorough verification of yield and performance issues than currently possible with existing verification flows. Kimotion's technology fits into any design flow, reducing the risk of re-spins and over-design by enabling designers to model, analyze, optimize and verify their circuits under environment and process variations.
Founded in 2001, Kilopass quickly introduced a new type of embedded non-volatile memory (NVM) technology called XPM (eXtra Permanent Memory), which is based on a CMOS antifuse one-time programmable (OTP) memory cell. Due to the fact that most — if not all — SOC designs now require some form of OTP memory to store encryption keys, access keys, manufacturing codes, and so forth, Kilopass would seem to be a company that's in the right place at the right time.
IPextreme (Booth #2464 [the ChipEstimate booth])
The little scamps at IPextreme deliver and support a wide-range of high-value IP originally developed by large semiconductor companies for applications such as consumer, automotive, industrial and networking.
Since its inception in 2004, the company — and especially its product portfolio — have been growing rapidly. The folks at IPextreme now sell and support IP sourced from Freescale, Infineon, NXP, Cypress and National Semiconductor, and they are announcing more IP partners and products all the time.
The guys and gals at Innovative Silicon develop and license ultra-dense Z-RAM (Zero-Capacitor DRAM) memory technology as IP for systems-on-chip (SOCs), microprocessors, and portable consumer applications requiring low power, high density and high speed.
The folks at Innovative Silicon believe that they're poised to hit "prime time" as companies migrate to 65nm — and even smaller geometries — and need to shrink their memory sizes to keep costs in check (this technology has already been licensed by AMD for use in its next-generation microprocessors).
The folks at IC Manage provide design management solutions for IC design, enabling companies to efficiently and reliably manage single and multi-site design efforts.
Founded in 2003 by Shiv Sikand and Dean Drako, IC Manage GDP is the first solution to offer design assembly, derivative management, and content delivery capabilities in addition to scalable, ultra-performance revision control, release, and configuration management. IC Manage GDP utilizes the Perforce engine and includes IT infrastructure integration for hot backup, high availability and disaster recovery for 24x7 enterprise availability.
In 2007 there will be nearly 89,000 FPGA design starts (some 25 times that of ASICs) according to Gartner/Dataquest. While verifying an FPGA is as challenging as any modern ASIC design, the little rascals at GateRocket claim that — until now — there hasn’t been a practical and economical solution to this daunting problem.
To address this, the folks at GateRocket have developed a mega-cool product called the RocketDrive. GateRocket’s software lets the verification engineer place any portions of the FPGA design into the RocketDrive and integrate it to the existing simulation platform. The result is the ability to exhaustively validate and test an FPGA design before committing to production, enabling shorter product development times, higher product quality, and improved performance.
Small is a relative term! Although still privately held, Forte has been relentless in paving the way to a higher level of abstraction for hardware design teams, which is a BIG task. Modestly claiming to be "the defacto standard for SystemC synthesis," Forte's high-level Cynthesizer synthesis technology lets design teams creating complex electronic systems from algorithmic designs using ASICs, FPGAs, and SOCs significantly reduce their overall design and verification time while improving quality of results.
This year at DAC, the folks at Forte say that they will be showing an integrated C to GDSII flow, a new library of SystemC behavioral design IP, and some major improvements to Cynthesizer's QoR.
Having attended DAC for more years than I care to remember, I've seen more than my share of canned demos. I've also learned to keep my mouth shut and to not say things like: "What happens if you click on this button?" because the answer is often that the entire system will "crash and burn" because the software is still wet behind its metaphorical ears.
So, one can only admire the plucky stance taken by the guys and gals at the golden timing constraints company Fishtail, because they've announced that they will offer customers the opportunity to verify and generate timing exceptions (false and multi-cycle paths) on their designs live at DAC. The idea is that you can bring actual designs you're working on and Fishtail will show you that your existing false and multi-cycle path definitions are fraught with mistakes (you will have to schedule a time with the folks at Fishtail). Furthermore, you'll leave the FishTail booth with formally generated timing exceptions for your designs that will have been independently proven to be correct. Wow!
EVE (Booth #4060)
EVE is a broad-line supplier of hardware-assisted verification platforms, including acceleration, fast emulation and easy FPGA prototyping. Recently, the folks at EVE introduced ZeBu-AX, offering plug-and-play, event-accurate mixed-language simulation acceleration. A scalable capacity lets ZeBu-AX handle designs that can reach up to 512 million ASIC gates. Its single-kernel runtime environment works in co-simulation with Synopsys VCS, Mentor Graphics QuestaSim, Cadence NC-Sim. It accelerates simulation from 10 to 1,000 times faster than any HDL simulator.
Although there are currently only around 20 people in the company, the guys and gals at DeFacTo (what a cool name) feel that they're poised to take off with their forthcoming DFT ('D' from "De", 'F' from "Fac", and 'T' from "To") offering.
Although no products have been formally announced, the stated intent of the company is to reproduce in the DFT space what previously happened in the design (synthesis) space — that is, to make RTL the de facto standard!
The chaps and chappesses at Coupling Wave Solutions have developed a solution for avoiding noise-related problems in chip design, dramatically reducing the impact of noise when combining analog, RF, and digital blocks in a single die or SiP.
A "new kid on the block," Coupling Wave Solutions claims to be the first EDA supplier to support the integration of sensitive — analog/ mixed-signal, RF — functions in digital IC designs by addressing interfering noise across the normal operation of the entire system. At this years DAC, Coupling Wave will be demonstrating a software platform to model the noise that's generated and propagated through the device’s substrate, interconnect, and package.
Founded in early 2006, Concurrent EDA has assembled a high caliber team of hardware and software engineers, all with extensive backgrounds in high performance application development and embedded systems design. Although their roots aren't in Silicon Valley, we've learned not to be surprised by great things coming from Pittsburgh-based companies in the engineering design automation industry (remember Ansoft, Ansys, and Neolinear?)
Concurrent EDA's product suite — which they plan to roll out officially later this year — utilizes a transaction-level analysis and synthesis engine to help embedded systems designers maximize application performance for a variety of technology targets, including FPGAs, DSPs, and multi-core processors. Although the folks at Concurrent EDA's aren’t talking too much, they will say that their approach eliminates the technical hurdle jumping required with other vendors' solutions for the C-to-gates design process.
Sad to relate, they won’t have a booth at DAC this year, but they will be at the show. If you would like to arrange a meeting at DAC, they say you can call the company at 412.687.2713 or e-mail them at info@concurrenteda.com.
CLK Design Automation is a new East Coast-based start-up company with 17 employees (14 of whom are in engineering). In a nutshell, the little rascals at CLK DA (and who is going to forget that name?) develop static timing, signal integrity, and power analysis tools for the design of high-performance microprocessors and advanced semiconductors.
The trick here is that CLK DA is pioneering a new generation of EDA tools based on what it claims is the first true threaded, incremental architecture. This patent-pending architecture enables the CLK Amber Analyzer to leverage the power of multi-core, multi-processor compute platforms to execute 10 to 20X faster than conventional tools. The same architecture also enables true incremental analysis for timing and signal integrity, where the ability to perform incremental analysis increases throughput 100X or more over existing design flows without any compromise in accuracy.
Since they hit the ground running in 2003, the guys and gals at Clear Shape have been trail-blazing the design-for-manufacturing (DFM) trail with practical, fast, full-chip, and silicon-accurate model-based physical and electrical DFM solutions.
Clear Shape’s Variability Platform lets designers perform variability-aware analysis and optimization based on true silicon behavior, thereby maximizing process technology utilization. The little ragamuffins currently have two products in their arsenal: InShape provides hotspot detection and fixing guidelines that let designers fix catastrophic issues before silicon, while OutPerform provides contour-based timing and leakage analysis and optimization to prevent unexpected electrical failures.
In ye olden days when I was a bright-eyed, bushy-tailed engineer, analog designs were implemented by designers drawing the polygons (geometric shapes) that would form the various layers used to create the transistor in silicon. As analog designs grew in complexity, designers started to use PCells (Parameterized Cells), each of which is a parameterized piece of code (a small program if you will) that can automatically draw all of the polygons on all of the layers required to implement an analog "thing."
The problem is that the vast majority of PCells in the world are written in a proprietary language called SKILL, and they cannot be interpreted by tools from other vendors. This is why the the guys and gals at Ciranova created PCell Xtreme, which — among other things — lets your existing PCells play with any appropriate OpenAccess-aware design tool.
You would have to have been living on another planet for the last couple of years to remain unaware of Calypto's main claim to fame — its SLEC (Sequential Logic Equivalence Checker) tool that can functionally compare different incarnations of a design, each of which may have varying numbers of pipeline stages, different timing characteristics, and be represented in different design languages.
At this year's DAC, you'll be able to see Calypto's new PowerPro CG (clock-gating) application — an automated RTL power optimization solution that reduces power with little or no impact on timing or area. Unlike power optimization tools working at the gate-level, PowerPro CG identifies clock-gating opportunities using sequential analysis of the design working with RTL and above where there's greater opportunity for power savings by gating more registers in the design and extending the duration of previously clock-gated registers.
The folks at Bluespec aren’t shy or retiring. They can look you in the eye and tell you (without laughing) that they have established themselves as the EDA industry's sole purveyor of ESL synthesis software. The reason for their boldness is that they are coming at things from a different direction than other folks. As opposed to leaping to a level of abstraction that is difficult to synthesize, they've created Bluespec SystemVerilog (BSV), which augments standard SystemVerilog with rules and rules-based interfaces that support complex concurrency and control across multiple shared resources and across modules. BSV also features high-level abstract types; powerful parameterization, static checking, and static elaboration; and advanced clock specification and management facilities. (They've also done the same thing to/with SystemC.) The result is the ability to capture both datapath and control constructs at a high level of abstraction that can be used to quickly and easily perform "what-if" design exploration, but that can also be efficiently synthesized.
With the recent announcement that its synthesis software has been tightly linked with EVE’s hardware-assisted verification platforms, the folks at Bluespec have further differentiated themselves, because their new ESL synthesizable transactors, testbenches, models, and designs run on emulation for high simulation speed with hardware accuracy early in the development cycle for architectural exploration, virtual prototyping, modeling, verification and implementation.
Although they leapt onto the stage only a few years ago in 2004, the folks at Blaze have already accomplished a lot for “little guys,” not the least that the company burst onto the scene with products, customers, and silicon success.
Parametric failures — chips that fail to meet timing and power specs — have been described as the most critical yield-limiting factor facing designers today. To address this, the guys and gals at Blaze came up with a unique solution — Electrical DFM — which slips seamlessly into the flow between design and manufacturing. The idea is that Blaze takes your taped-out GDSII, analyzes it, and adds annotations that direct downstream tools in the manufacturing process to make your design more implementable, with a double-digit increase in parametric yield. (Electrical DFM can also increase your design's performance, reduce its power consumption, and make your smile brighter!) In March of this year Blaze merged with Aprio Technologies to complete its Electrical DFM technology portfolio.
The chaps and chappesses at Berkeley Design Automation have super-sized brains with go-faster stripes painted on the size! How else could they create tools that deliver full Spice accuracy 5 to10X faster than any other tools for circuit simulation: for example, Analog (FastSpice), periodic analysis (RF FastSpice), and phase noise analysis (PLL Noise Analyzer).
Berkeley's proprietary Precision Circuit Analysis technology combines the accuracy, performance, and robustness needed to thoroughly verify GHz designs in nanometer-scale silicon.
Azuro (Booth #6660)
Azuro's claim to fame is "clock implementation for nanometer designs." The folks at Azuro are enabling electronics companies around the world to build high-performance, low-power semiconductor chips with higher productivity than ever before. Its flagship product, PowerCentric, is said to be the industry’s first multi-objective clock implementation solution. PowerCentric replaces clock tree synthesis (CTS) and post-CTS optimization steps within digital design flows while comprehensively addressing power, timing, and variability.
Multi-voltage designs have become the norm to control power in today's SOCs. The problem is that the use of these multi-voltage techniques has increased verification complexity; traditional verification solutions can provide inadequate coverage of the power states and can result in silicon failures or failures during field operation.
To address this, the folks at ArchPro provide EDA products that are tailored to meet the low-power and multi-voltage power management challenges facing SOCs at 90nm and below. Proven across multiple process nodes including 90nm and 65nm with design sizes of 200 million transistors, ArchPro's multi-voltage design tools feature verified advanced power reduction techniques such as power gating, substrate biasing and dynamic voltage frequency scaling (DVFS).
By Clive (Max) Maxfield. Max is president of TechBites Interactive (www.TechBites.com), a marketing consultancy firm specializing in high-tech. In addition to authoring "Bebop to the Boolean Boogie (An Unconventional Guide to Electronics)" and "The Design Warrior's Guide to FPGAs (Devices, Tools, and Flows)", Max is the co-author of How Computers Do Math (ISBN: 0471732788) featuring the pedagogical and phantasmagorical virtual DIY Calculator. In addition to being a hero, trendsetter, and leader of fashion, Max is widely regarded as being an expert in all aspects of computing and electronics (at least by his mother). Max was once referred to as "an industry notable" and a "semiconductor design expert" by someone famous who wasn't prompted, coerced, or remunerated in any way.
