Changing the Paradigm of Electrical Test
The test of electronic circuits has been a key topic in the industry since the first transistor was developed, and today it is as relevant as ever. Most of us agree that product testing is absolutely necessary: as part of design validation, as a quality indicator for manufacturing process control, or for the detection of defective products prior to shipping them to a customer. We do have certain requirements that should be met, however, by our test solutions: test development and execution should be fully automated and should be done in essentially no time, we want the test equipment to be very inexpensive, and we want a fault coverage of 100%.
Read the entire article from GOEPEL electronic GmbH on SOCcentral.
New IJTAG Standard Simplifies SOC Verification and Test Processes
Modern SOCs are a complex mix of embedded-IP cores, customized logic provided by the chip supplier and a myriad of communication interfaces. SOC designers have found that accessing instruments embedded into their chips and embedding their own instruments into their devices is the best way to test and verify that a device meets its specifications, is functioning properly and achieves its performance goals. As a result, embedded instruments have become central to SOC design-for-test (DFT), design-for-debug (DFD), design-for-manufacturing (DFM) and verification strategies (usually collectively termed DFx).
Read the entire article from ASSET InterTech, Inc. on SOCcentral.
Vendor-Independent RTL Memory BIST Insertion and Verification
ASIC vendors have traditionally incorporated built-in self-test (BIST) and repair solutions in their customers' gate-level netlists. This used to be the common industry practice for technology nodes of 65nm and older. Designers were comfortable writing in-house Perl scripts to replace memory instances with combined memory-BIST (MBIST) instances and make the necessary connections. But for more-advanced technology nodes, it is becoming common practice to share a BIST engine with multiple memories — technology permitting — and insert hierarchical BIST IP along with accurate connections. As teams design larger chips and move to more advanced nodes, the tried-and-true practices will not be as efficient.
Read the entire article from Atrenta, Inc. on SOCcentral.
The Need for a Comprehensive SOC Test Platform
Silicon test is the final arbiter that determines if an integrated circuit should be packaged and ultimately shipped to a customer or is defective and should be scrapped. Consequently, a poor test strategy and methodology can have a significant impact on the success of your product. If the test doesn't cover all possible design structures or doesn't provide high enough test coverage, then you could be unwittingly shipping bad devices (that pass the test) to your customers. If you have more tests than needed, or your test is overly constrained, your test cost could be unnecessarily eating into your profit margin. With their diverse structures and almost unfathomable complexity, a modern day system-on-chip (SOC) amplifies the challenge of developing an effective test. The need for a comprehensive test platform to address and manage these challenges has never been so tantamount to business success.
Read the entire article from Mentor Graphics Corp. on SOCcentral.
Comparing ATPG Runs
The purpose of integrated circuit test is to help segregate good devices from those that are defective to improve manufacturing yield — reducing defective parts per million to as low as 100 defective parts per million and thereby increasing shipped yield. These low-defect levels are achieved through automatic test pattern generation (ATPG) algorithms that target faults that are abstractions of defects. By making some design modifications to assist ATPG, it is possible to automate the task of targeting defect-based faults and achieve high fault coverage/efficiency with a reasonable number of test patterns.
Read the entire article from Synopsys, Inc. on SOCcentral.