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Boundary Scan Tutorial

In this tutorial, you will learn the basic elements of boundary-scan architecture — where it came from, what problems it solves, and its implications on the design of an integrated-circuit device. This tutorial also provides an overview of the data standards applicable to the boundary-scan architecture and an overview of the software tools available to perform boundary-scan-based tests.

Read the entire tutorial on the ASSET InterTech, Inc. website.

The New DFT Reality at 90nm

Design-For-Test (DFT) is at a tipping point. A tipping point is when changes in behavior or perception reach a critical mass, creating a whole new reality. You know you are on the edge of a tipping point when undeniable events cause people to reframe an issue. The new reality in DFT is that pseudorandom Built- In-Self-Test (BIST) is displacing classical Automatic Test Pattern Generation (ATPG) based methodologies.

IC vendors designing at 0.13µm are already experiencing a decline in yield for complex SoC devices. It is anticipated the problem will only get worse at 90nm, 65nm and beyond. In addition, field returns at these smaller geometries are increasing at an alarming rate. The analysis of these yield losses and field returns indicate performance issues based on design and process interactions are the main causes. These failures are related to speed faults, interconnect parasitics, and leakage-sensitive factors, which can euphemistically be thought of as the analog-type behavior of digital circuits. Often these faults are difficult to model.

While many of the faulty devices are identified in manufacturing at probe or final test, there are increasing problems with products going into the field with insufficient test coverage. This results in costly field failures for the end-user system companies and has a major negative impact on margins. In many cases the failure analysis of these field returns results in "no problem found". (NPF)

The primary cause for an NPF result is that the test is incomplete because the defect coverage is too low, thus manufacturing test cannot identify the faulty parts. Another cause is that testing is not always applied under the same functional conditions that prevail in the end application or system. This may be the result of noise, crosstalk, voltage, temperature, humidity and a multitude of other difficult to model factors. A third cause is insufficient system design margins.

Read the entire article by LogicVision, Inc. on SOCcentral.

Why Haven't EDA Vendors Given Us DFT at the Register Transfer Level?

Design for test (DFT) solutions are increasingly indispensable to the chip designer, but what does DFT really mean, and what sort of relief does it provide? And why are solutions stuck at the gate level instead of at the register transfer level (RTL), where main design decisions are taken and important design requirements such as reuse are considered?

The cost associated with manufacturing testing of integrated circuits is climbing. The International Technology Roadmap Semiconductors reports that the semiconductor industry has reached a point where testing a chip costs as much as manufacturing it. With greater functionality being packed into each design, both the time required to test each integrated circuit (IC) and the cost of the necessary testing equipment keep increasing. Design for test, which essentially means constructing designs with easy testability in mind, is key to solving the problems of both time and expense.

Today, it is mandatory to consider testability issues very early in the design process and it is not acceptable for an RTL designer to deliver synthesizable code in Verilog or VHDL with testability problems (that is, with test vectors of poor quality). Yet qualification of the quality of test vectors is still performed at the gate level, which means that RTL designers must run the synthesis process and iterate around this time-consuming process before delivering testable RTL code.

Read the entire article by DeFacTo Technologies, Inc. on SOCcentral.

When Probing Goes in the Chip

Today's system-on-chip designs create a situation where system complexity, coupled with time-to-market pressure, make the debug and characterization of these systems more critical and challenging than ever. At the same time the physical implementation in making the traditional measurements needed has become nearly impossible. The answer is instrumenting SOC designs with on-chip probing technology. BGA packaging brought with it a new era where probing individual components directly became impossible. Probing innovation moved from an emphasis on connecting with individual packages to PC board connectivity. And while today's physical probing solutions can accurately measure busses running in excess of 1 GHz on PC boards, the technology has not addressed the need for the probes to extend inside the chip. Why the need? With the adoption of digital systems-on-chip in full swing, entire sub-systems that used to be implemented on circuit boards are realized inside a single device. Since the individual devices and busses that interconnect them are now "buried" inside the chip, it is no longer possible to probe and acquire data for integration of hardware subsystems, hardware and software integration, and performance characterization.

Read the entire article by Agilent Technologies on SOCcentral.

Generating Faster-than-at-Speed Delay Tests with On Product Clock Generation

Nanometer technologies contain newer types of defects that are delay sensitive and can no longer be detected with traditional stuck-at tests. High impedance shorts, resistive vias and bridges, in-line resistance, and crosstalk between signals are some of these newer types of defects that are commonly seen in today's nanometer designs. Since many of these newer defects cause faulty timing behavior rather than faulty logic behavior, they can be effectively caught only by applying the tests at system speeds. This has led to the required use of delay-based fault models in Automated Test Pattern Generators (ATPG) to target these defect types. Transition faults and path-delay are two delay-based fault models that are widely used today while performing at-speed testing.

Studies have proven that the detection of defective parts by manufacturing delay tests test depends on the test timing of the launch and capture clocks. Fewer defects are detected when tests are run at speeds slower than the operating speed of the device (under normal operating voltage). As demonstrated in, delay defects are affecting chip quality and scan based delay test is the most efficient and most effective chip manufacturing test to address the problem. In many applications, the launch and capture clocks need to be generated on-chip, via the use of test clock control logic is usually referred to as On Product Clock Generation for test (OPCG).

In many applications, delay tests that run at the clock domain speed are not sufficient. To detect small delay defects, the tests need to run at the tightest possible timing, and for many transition faults that means running faster than at-speed. The OPCG solution needs to support the generation of clock pulses with a duty cycle that is faster than the actual clock domain speed.

Read the entire article by Cadence Design Systems, Inc. on SOCcentral.

Comparing ATPG Runs

The purpose of integrated circuit test is to help segregate good devices from those that are defective to improve manufacturing yield -- reducing defective parts per million to as low as 100 defective parts per million and thereby increasing shipped yield.

These low-defect levels are achieved through automatic test pattern generation (ATPG) algorithms that target faults that are abstractions of defects. By making some design modifications to assist ATPG, it is possible to automate the task of targeting defect-based faults and achieve high fault coverage/efficiency with a reasonable number of test patterns. Like any other automation activities completed in ATPG, the results of this process can then be scrutinized in benchmarks, and tool improvements can be monitored over successive generations of the product to achieve more efficient IC test automation.

Read the entire article by Synopsys, Inc. on SOCcentral.

High Octane ATPG

Eight years ago, test cost for high-performance devices such as microprocessors was a serious concern. The International Technology Roadmap for Semiconductors (ITRS) published an infamous diagram indicating a trend of deep concern for the industry. The trend predicted test cost would become a significant majority of overall manufacturing cost (see Figure 1).

The result of these predictions was a mobilization of the industry to head off a situation where test costs could impede Moore's Law. The challenge brought forth by the ITRS report caused test tool suppliers to take notice. Specifically, they began to see this developing situation as an opportunity for increased utilization of design-for-test (DFT) methodologies. Ultimately, this projected trend never became a reality, and more recent ITRS reports show that test costs remain at a very manageable level. In fact, because of breakthrough technical advances, DFT is now being called upon to take an ever more prominent role in improving overall product quality.

Read the entire article by Mentor Graphics Corp. on SOCcentral.