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 Category: Special Topics: Reconfigurable Computing: Friday, September 10, 2010

Featured Articles

Configurable Processors: The Next Evolutionary Step for Microprocessors

The course of electronic systems design changed irreversibly on November 15, 1971 when Intel introduced the first commercial microprocessor, the 4004. Before that date, system design consisted of linking many hardwired blocks, some analog and some digital, with point-to-point connections. After the 4004 microprocessor’s public release, electronic system design began to change. The first and most obvious change was the injection of software or firmware into the system-design lexicon. Over the next 30 years, microprocessor-based design has become the nearly universal approach to systems design and, with the advent of practical 8-bit microprocessors in the mid 1970s, microprocessors began to permeate system design. Ever since that time, microprocessor vendors have been under great pressure to constantly increase their products’ performance as system designers think of more tasks to execute on processors.

Read the entire article from Tensilica, Inc. on SOCcentral.

Configurable Processors: What, Why, How?

A new type of processor core has been getting a lot of attention lately - a processor you can tailor for a specific application. Configurable processor cores are much faster and can do much more than standard embedded microprocessor cores. Some can even be used instead of hand-coding RTL in IC designs, which greatly speeds SOC development.

What is a configurable processor? What can configurable processor cores do? Why would anyone want to use this type of processor? How can a configurable processor core replace RTL coding in the design of an SOC? These questions and more are answered in this article.

Most popular embedded microprocessor architectures-such as the ARM, MIPS, and PowerPC processors-were originally designed in the 1980s as stand-alone chips. These general-purpose architectures are nearly universally applicable over a wide range of applications because they are good at executing a very wide range of algorithms. However, SOC designers often have to speed up critical portions of their design in hardware because general-purpose processor cores execute some algorithms too slowly to meet performance goals. Even DSP architectures can't match the speed of a custom-tailored hardware.

Read the entire article from Tensilica, Inc. on SOCcentral.

Reconfigurable Systems Craft a New Breed Of “Soft Appliances” that Deliver Topnotch Performance

As chip designs migrate down the process roadmap from 130 to 90 to 65nm and beyond, the cost of implementing a system-on-chip (SOC) solution doubles to triples at each smaller process node. For example, at 130-nm a typical high-end design from start to finish might cost about $8 million, while at 90nm it might cost close to $20 million, and at 65nm, most estimates peg the cost of a high-end SoC at close to $45 million.

The higher cost to design and implement a chip at each process node is forcing companies to rethink their SOC development plans since the number of chips sold for each design must be in the millions to keep the amortized development cost per chip to a reasonable level. Aside from the consumer and automotive markets, there are few commercial markets (networking, storage, scientific computing, etc.) that have the volumes to justify the high SOC development costs.

When chip applications, such as specialized accelerators and application unique functions, don’t create a demand for millions of chips, a programmable off-the-shelf solution rather than an SOC design may be a more cost-effective and more timely alternative. Such a “soft appliance” can reduce system development cost, shorten the time to market, reduce system maintenance, and provide a simple upgrade path. Today’s large field-programmable gate arrays (FPGAs) are at the heart of such systems. The latest generations of FPGAs can now deliver system complexity levels (millions of gates and megabits of memory) and performance levels (over 1 billion integer multiply-accumulate operations/s) that suit them for many of the lower-volume applications that cannot justify the development cost of an SoC solution.

Read the entire article from DRC Computer Corp. on SOCcentral.

Designer's Mall

SOCcentral feature articles about Reconfigurable Processors & Computing

Why High MHz Does Not Mean High Performance (5/31/2007)
Configurable Processors: The Next Evolutionary Step for Microprocessors (1/8/2007)
Reconfigurable Systems Craft a New Breed Of “Soft Appliances” that Deliver Topnotch Performance (1/8/2007)
The Future of Configurable Microprocessing (9/7/2005)
Configurable Processors: What, Why, How? (6/1/2005)
Software-Configurable Processors on the Rise (6/1/2005)

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SOCcentral news items about Reconfigurable Processors & Computing

Xilinx Improves Design Flow for Partial-Reconfiguration FPGA Technology with ISE Design Suite 12.2 (7/28/2010)
Chelsio Communications Licenses Tensilica's Xtensa LX Customizable Dataplane Processor Core for 10-Gbit Ethernet (7/20/2010)
Multiple Tensilica IP Cores Power NEC, Fujitsu and Panasonic Mobile Communications LTE Handset SOC for Major Japanese Wireless Carrier (3/22/2010)
CoWare and Tensilica Deliver Software-Development Solution for Multi-Core Tensilica-Based Platforms (12/18/2009)
Tensilica Delivers New Design Flow Support for Synopsys' Galaxy Implementation Platform Technologies (12/9/2009)
New Tensilica DPU Family Delivers 10-GMAC/sec DSP Performance, Tops 1-GHz Mark (11/2/2009)
Tensilica Introduces Small, Ultra-Low-Power Dataplane Processor Core for Deeply Embedded Control (10/19/2009)
Tata Elxsi and Tensilica Announce RoS-ES RTOS for Diamond Standard and Xtensa Customizable DPUs (10/16/2009)
IMEC's Multithreaded ADRES Processor Architecture Ready for Licensing (10/8/2009)
siXis Introduces Reconfigurable Computing Platform (10/1/2009)
Recore Systems Receives $3 Million Funding (9/21/2009)
Element CXI Announces nGEN Elemental Computing Array, a Fully Reconfigurable Platform for 4G Networks (9/17/2009)

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Magazine & Journal articles on Reconfigurable Processors & Computing

Continuous Integration of Complex Reconfigurable Systems Design & Reuse (5/20/2010)
Reconfigurable Computing Prospects on the Rise HPCwire (12/3/2008)
How to Transform Silicon with Dynamic Reconfiguration Programmable Logic DesignLine (10/1/2008)
Building a Configurable Embedded Processor Embedded Systems Design (embedded.com) (9/9/2008)
PCI Express Bridging Options Enable FPGA-Based Configurable Computing Programmable Logic DesignLine (9/8/2008)
Reconfigurable Computing: Custom Supercomputers on Demand? Programmable Logic DesignLine (4/15/2008)
Reconfigurable Computing for Acceleration in High-performance Computing FPGA and Programmable Logic Journal (2/26/2008)
Optimizing GPS, Audio/Video Streaming Algorithm Designs with Atmel's Customizable CAP MCUs Embedded Systems Design (embedded.com) (10/26/2007)
FPGA-Based Hardware Acceleration of C/C++ Based Applications: Part 4 Programmable Logic DesignLine (10/24/2007)
FPGA-based Hardware Acceleration of C/C++ Based Applications: Part 2 Programmable Logic DesignLine (8/1/2007)
Why High MHz Does Not Mean High Performance SOCcentral (5/31/2007)
Configurable Processors: The Next Evolutionary Step for Microprocessors SOCcentral (1/8/2007)
Reconfigurable Systems Craft a New Breed Of “Soft Appliances” that Deliver Topnotch Performance SOCcentral (1/8/2007)
FPGA Partial Reconfiguration Mitigates Variability eeDesign (EE Times EDA News) (4/3/2006)
Reconfigurable Computing in Real-World Applications FPGA and Programmable Logic Journal (2/7/2006)
The Future of Configurable Microprocessing SOCcentral (9/7/2005)
Denser, Faster Chips Deliver Knockout DSP Performance Electronic Design Magazine (7/7/2005)
Configurable Processors: What, Why, How? SOCcentral (6/1/2005)
Software-Configurable Processors on the Rise SOCcentral (6/1/2005)
On the Death of Microprocessors Embedded Systems Design(embedded.com) (8/19/2004)
Reconfigurable Illogic Embedded Systems Design (embedded.com) (8/19/2004)

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Tutorials, White Papers and Conference Papers on Reconfigurable Processors & Computing

A Hardware-Software Partitioning and Scheduling Algorithm for Dynamically Reconfigurable Embedded Systems IMEC
An Efficient Algorithm for Finding Empty Space for Online FPGA Placement Design Automation Conference (DAC)
Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture IMEC
DRESC: A Retargetable Compiler for Coarse-Grained Reconfigurable Architectures IMEC
Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling IMEC
FITS: Framework-Based Instruction-Set Tuning Synthesis for Embedded Application Specific Processors Design Automation Conference (DAC)
How to Increase ASICs and SOC Computational Performance with Long-Word Processors Tensilica, Inc.
Reconfiguration for Reliability Tools Synplicity, Inc.
RISPP: Rotating Instruction Set Processing Platform (44.1) Design Automation Conference (DAC)
Selective Bandwidth and Resource Management in Scheduling for Dynamically Reconfigurable Architectures (43.2) Design Automation Conference (DAC)
Specific Scheduling Support to Minimize the Reconfiguration Overhead of Dynamically Reconfigurable Hardware Design Automation Conference (DAC)
The What, Why, and How of Configurable Processors Tensilica, Inc.
Virtual Memory Window for Application-Specific Reconfigurable Coprocessors Design Automation Conference (DAC)

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