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 Category: Special Topics: Design for Manufacturing: Monday, May 20, 2013
 Design for Manufacturing

Featured Articles

Profiling Defect Sites for Yield Improvement

Profiling defect sites is a technique made simple with the development of pattern matching. A suspect location may be broken down into the individual patterns of its whole, enabling designers to perform analysis on each pattern to identify which pieces may be robust or problematic to manufacture. There are multiple ways to perform defect-site profiling: breaking up pieces of a site into different hierarchies based on repeated structures or specified features, using an area/ density-based algorithm to split up a site into pieces, or covering a design with a grid and taking window clippings of the design for each grid space. Whatever method is used, the key is to define a simple, yet distinct, feature such that the design team will be able to identify most, if not all, potential locations of defects.

Read the entire article from Mentor Graphics Corp. on SOCcentral.

The New Standard for 32/22-nm IC Physical Design and Sign-Off

With the advent of advanced process nodes, IC design teams have an increasing ability to pack more functionality and performance into state-of-the art SOCs. However, design challenges are growing as we push the limits of complexity, size, power reduction, and manufacturing scaling. Designers need a new generation of physical design tools to effectively address these issues. Starting at 45/40nm, the increasing complexity of DRC and DFM rules began to stress traditional physical design flows. This trend is expected to continue and worsen at the 32-nm and 22-nm nodes, where manufacturing closure may become a serious bottleneck in design schedules.

Read the entire article from Mentor Graphics Corp. on SOCcentral.

Seeing Is Believing: How Visualization Simplifies IC DRC

As physical features and ICs shrink, lithographic and field effects expand, resulting in more numerous and often subtle design-for-manufacturing (DFM) issues. Simple linear spacing, length and width measurements between adjacent features are no longer sufficient. IC design rules now must take into account many three-dimensional geometric measurements related by complex functions to determine if a design is manufacturable at leading-edge process nodes.

Read the entire article from Mentor Graphics Corp. on SOCcentral.

Designer's Mall

SOCcentral news items about Design for Manufacturing

Cadence and GlobalFoundries Collaborate to Improve DFM Sign-Off for 20- and 14-nm Nodes (4/29/2013)
KLA-Tencor Announces Novel Defect Discovery and Monitoring Technology (4/24/2013)
Study Says 20-nm SRAM Design Could Suffer from the Interplay Between Statistical Variability and Reliability (4/22/2013)
Next-Generation ODB++ Intelligent Data Format for Enhanced Modeling to Support DFM, Fabrication, Assembly and Test Now Available (2/14/2013)
ProPlus Now Offering Integrated Design-for-Yield Product Portfolio (2/7/2013)
Mentor Graphics Announces Comprehensive Design Enablement Platform for Samsung's 14-nm IC-Manufacturing Process (12/24/2012)
Synopsys and TSMC Enable Lithography Compliance Checking for 20nm (11/14/2012)
Qualtera Launches Silicondash to Speed Semiconductor Yield, Product and Test Engineering (10/23/2012)
ProPlus Design Solutions Unveils Design-for-Yield Software (9/25/2012)
Latest Release of Synopsys IC Validator Delivers Faster Manufacturing Compliance at 20nm and Below (9/6/2012)
Mentor Graphics Calibre Pattern Matching Enables Advanced Checking of TSMC 20-nm Designs (6/4/2012)
Mentor Graphics Receives Certification for TSMC 20-nm Process (6/4/2012)
GlobalFoundries Selects Synopsys' Yield Explorer for Faster Yield Ramp (5/30/2012)
Mentor Graphics Calibre SmartFill Addresses TSMC 20-nm Fill Requirements (5/30/2012)
Mentor Graphics and GlobalFoundries Collaborate on 20-nm Fill Solutions Based on Calibre SmartFill (5/29/2012)
Mentor DFM Analysis Service Delivers Calibre Litho Checks for TSMC 40-nm and 28-nm Processes (5/24/2012)

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Magazine & Journal articles on Design for Manufacturing

Reclaiming Lost Yield Through Methodical Power-Integrity Optimization EE Times EDA Designline (4/1/2013)
Advanced Yield-Enhancement Technique: Lithography-Friendly Design EE Times EDA Designline (3/4/2013)
Profiling Defect Sites for Yield Improvement SOCcentral (11/9/2012)
Design for Manufacturability: An Overview Design & Reuse (7/30/2012)
Diagnostic and Repair Tools for Embedded Memory Boost SOC Yields EE Times Memory Designline (7/23/2012)
Effective Finger-Pointing: The Art of Modern Yield Analysis Tech Design Forum (5/22/2012)
Design for Reliability: The Golden Age of Simulation-Driven Product Design EE Times EDA Designline (5/7/2012)
Test-Driven Development for Embedded C: Why Debug? EDN Magazine (3/15/2012)
Successful Adoption of DFM EE Times EDA Designline (2/6/2012)
Critical Area Analysis and Memory Redundancy EE Times EDA Designline (12/19/2011)
Minimizing Yield Fallout by Avoiding Over and Under At-Speed Testing EE Times Embedded (9/30/2011)
Realizing the Promise of Electrically-Aware Custom IC Design Electronic Design Magazine (8/9/2011)
The (Design) House Always Wins: How DFM Improves the Odds of Tape-Out Success Chip Design Magazine (4/1/2011)
The Traditional Approach to IC Implementation and Its Problems Electronic Design Magazine (3/11/2011)
Evolution of Manufacturing Closure for Advanced Nodes: Part 3 EE Times EDA Designline (3/7/2011)
Evolution of Manufacturing Closure for Advanced Nodes: Part 2 EE Times EDA Designline (2/28/2011)
Evolution of Manufacturing Closure for Advanced Nodes: Part 1 EE Times EDA Designline (2/21/2011)
Ease Production at 65nm with DFM EE Times EDA Designline (2/15/2011)
The Need for a Comprehensive SOC Test Platform SOCcentral (1/16/2011)
Verification Challenges and eDFM in Digital Designs DAC Knowledge Center (1/5/2011)
Parametric yield: Do You Know What You Miss? EE Times EDA Designline (11/10/2010)
Seeing Is Believing: How Visualization Simplifies IC DRC SOCcentral (9/1/2010)
Optimizing the Manufacturing Test Program, Data Collection, and Diagnosis for Yield Analysis EE Times EDA Designline (8/31/2010)
The New Standard for 32-nm IC Physical Design and Signoff SOCcentral (3/11/2010)
Design for Diagnosis to Improve IC Yield EE Times EDA Designline (1/25/2010)
In-Design Metal-Fill Key to Physical-Verification Turn-Around Time for Advanced IC Designs EE Times EDA Designline (12/8/2009)
Probabilistic Timing Analysis SOCcentral (10/31/2009)
DFM-Compliant IP: Why You Need It, How You Get It SOCcentral (9/9/2009)
Analog and Mixed-Signal IC Debug SOCcentral (8/2/2009)
Design for Manufacturing Sheds the Hype Electronic Design Magazine (6/11/2009)
Manufacturing Compliance: It’s Your Job Printed Circuit Design & Fab (3/1/2009)
Challenges in 45-nm Physical Design SOCcentral (11/6/2008)
Tips to Improve Manufacturability Printed Circuit Design & Fab (11/1/2008)
… But Will It Work? SOCcentral (9/2/2008)
A Comprehensive Approach to Manufacturing Variability SOCcentral (9/2/2008)
Manufacturing Concerns Move Up the Design Cycle SOCcentral (9/2/2008)
Solving the DFM Interoperability Crisis SOCcentral (9/2/2008)
The Shifting Landscape of DFM SOCcentral (9/2/2008)
Improving Fabrication Yields By Design Printed Circuit Design & Fab (4/1/2008)
Achieving Yield in the Nanometer Age EE Times EDA Designline (12/17/2007)
Using DFM Routing to Impact Design Performance and Yield EE Times EDA Designline (12/4/2007)
Applying Volume Diagnostics to Accelerate Yield Learning SOCcentral (11/5/2007)
Sign-Off for Manufacturability EE Times EDA Designline (10/8/2007)
How Low Can You Go? A Look at 45-nm IC Design Challenges EDN Magazine (9/13/2007)
Process Intelligent Modeling and Statistical STA improve DFM EE Times EDA Designline (9/11/2007)
Design For Manufacturing: Still not Ready for Prime Time? Electronic Design Magazine (8/16/2007)
Silicon Validation via LFD Simulation SOCcentral (8/6/2007)
In the Eye of the DFM/DFY Storm EE Times EDA Designline (5/25/2007)
Measuring Scan Compression Performance EE Times EDA Designline (5/21/2007)
Model-Based Metal Fill Optimizes Planarization and Increases Yield EE Times EDA Designline (3/22/2007)
Design for Variability: Design, Process, and Manufacturing Variations in Physical Design EE Times EDA Designline (3/19/2007)
Test Data Provides Yield Improvement Metrics EE Times EDA Designline (1/22/2007)
Sifting the DFM Players EDN Magazine (8/17/2006)
DFM at DAC SOCcentral (7/14/2006)
Is Chip Design Different After 90nm? EDN Magazine (7/6/2006)
Critical Area: A Metric for Yield Optimizations in Physical Design SOCcentral (6/5/2006)
Strategies to Prevent IC Failures in Volume Production SOCcentral (5/18/2006)
Critical Area Optimizations Improve IC Yields eeDesign (EE Times EDA News) (1/9/2006)
Yield Challenges Require New DFM Approach eeDesign (EE Times EDA News) (11/21/2005)
Managing Variations in IC Physical Design eeDesign (EE Times EDA News) (10/24/2005)
It’s All About the Routing, Stupid! SOCcentral (10/17/2005)
Test Takes New Role in Yield Improvement eeDesign (EE Times EDA News) (10/17/2005)
The Truth About Design for Manufacturing Electronic Design Magazine (9/29/2005)
DFM: What Do the Letters Really Mean? SOCcentral (7/22/2005)
EDA Can't Afford to Ignore Test Chips Any Longer Electronic Design Magazine (7/15/2005)
Improving Yield in RTL-to-GDSII Flows eeDesign (EE Times EDA News) (7/11/2005)
EDA Tools Aim at Improving Yield SOCcentral (7/1/2005)
Improving Test Through Real-Time Information SOCcentral (7/1/2005)
Model-Based Approach Allows Design for Yield eeDesign (EE Times EDA News) (4/18/2005)
What Designers Need to Know About TCAD eeDesign (EE Times EDA News) (4/4/2005)
Take Designs from Algorithms to Artwork Chip Design Magazine (3/1/2005)
Nanometer Yield Enhancement Begins in the Design Phase Electronic Design Magazine (1/20/2005)
How Statistical Sensitivity Makes Designs Manufacturable eeDesign (EE Times EDA News) (12/9/2004)
Design for Volume Chip Design Magazine (11/1/2004)
Accelerating SOC Design While Reducing Costs SOCcentral (10/25/2004)
Mano a Mano with Manufacturing EDN Magazine (10/25/2004)
How Diagnostics Accelerate Nanometer Yield Ramp eeDesign (EE Times EDA News) (10/1/2004)
Improving Yields without Compromising Area eeDesign (EE Times EDA News) (8/13/2004)
If You Can't Build It, It Isn't Worth Much EDN Magazine (4/1/2004)
Design-for-Manufacturing Demands New Infrastructure Electronic Engineering Times (EE Times) (1/15/2004)
How Designers Can Increase Parametric Yield eeDesign (EE Times EDA News) (11/21/2003)

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Tutorials, White Papers & Application Notes on Design for Manufacturing

Accelerating Nanometer Yield Ramp with Yield Diagnostics Cadence Design Systems, Inc.
Characterization-to-Silicon DFM Design Flow Magma Design Automation, Inc.
Embedded Instrumentation: The Future of Advanced Design Validation, Test and Debug ASSET InterTech, Inc.
Requirements for True DFM and DFY Magma Design Automation, Inc.
The DFM Pandemic: How Many Chips Have to Die? Pyxis Technology, Inc.
Understanding Design for Yield Ponte Solutions, Inc.
Using Boundary Scan to Link Design and Manufacturing Test ASSET InterTech, Inc.
Variation Analysis and Design for Custom ICs Gary Smith EDA
Variation-Aware Custom IC Design Report 2011 Solido Design Automation, Inc.
We Haven’t Survived 65nm: We’re Just in the Eye of the Storm! Pyxis Technology, Inc.

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