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Hard Macro Placement in Complex SoC Design
Advanced process nodes enable the implementation of highly complex system on chips (SoCs) and multimillion-gate designs such as memories, processor cores, analog circuitry, DSP cores, and PLLs. For these large, complex designs, designers are using more hard macros to help speed logic-gate placement and to alleviate some tool-capacity challenges. Most of the logic gates - and, therefore, most hard macros used to place these gates - are dedicated to memories.
To succeed in their role, physical designers must deliver a competitive product “right” to market: the right features and functionality at the right time and cost. This means that the die size (area) cannot be too large, the design cost must remain within the range of profitability, the design must operate at its target frequency, and the entire design — from concept to silicon — must be delivered on time. As a result, accurate hard macro placement can make the difference between a design success and a design failure, and is becoming mission-critical to SoC design.
In this article, we look at the challenges — and solution — to accurate hard macro placement.
Read the entire article by Synopsys, Inc. on SOCcentral.
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