Featured Articles

Hard Macro Placement in Complex SoC Design

Advanced process nodes enable the implementation of highly complex system on chips (SoCs) and multimillion-gate designs such as memories, processor cores, analog circuitry, DSP cores, and PLLs. For these large, complex designs, designers are using more hard macros to help speed logic-gate placement and to alleviate some tool-capacity challenges. Most of the logic gates - and, therefore, most hard macros used to place these gates - are dedicated to memories.

To succeed in their role, physical designers must deliver a competitive product “right” to market: the right features and functionality at the right time and cost. This means that the die size (area) cannot be too large, the design cost must remain within the range of profitability, the design must operate at its target frequency, and the entire design — from concept to silicon — must be delivered on time. As a result, accurate hard macro placement can make the difference between a design success and a design failure, and is becoming mission-critical to SoC design.

In this article, we look at the challenges — and solution — to accurate hard macro placement.

Read the entire Synopsys, Inc. article on SOCcentral.

Moore’s Law and the Need for a Revolution in Floorplanning Methodology

Now, with Moore's Law racing forward at an accelerated pace, increasing transistor counts, emerging design challenges and sophisticated analysis requirements are making it difficult to meet performance and time-to-market goals. This article will describe problems with current approaches to floorplanning and why a revolutionary approach to floorplanning must take place if we are to continue to maintain and grow the rate of design starts and meet available fabrication capacity.

Read the entire Magma Design Automation, Inc. article on SOCcentral.

It’s All About the Routing, Stupid!

It’s no secret that the task of designing and manufacturing today’s extremely complex multi-million gate ASICs and SoCs is becoming increasingly problematical. The message is taking hold that the design community can no longer ignore the issues of yield and manufacturability. The question in the industry has evolved from "why should my design team worry about manufacturability and yield?" to "what should my design team do about manufacturability and yield and where should I start?"

Unfortunately for the designer, the industry has not yet provided a magic "knob" that designers can turn to adjust the yield of their designs. Most SoC designers have three main things they can control: the architecture of the design, the choice of building blocks they use to create the design, and the routing that hooks everything together.

Read the entire Pyxis Technology, Inc. article on SOCcentral.