Category: Vendor Webcasts: Upcoming Webcasts:

Friday, May 24, 2013

Shorter, Better and Easier PCIe and NVMe Verification Flow with Advanced Technologies Featured

Sponsor: Cadence Design Systems, Inc.
Webcaster: EE Times Education & Training

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July 25, 2012 -- This webinar will present the technical challenges of advanced PCIe-based design verification, and the latest methodologies and tools to address them. Real-world case studies, describing how PCIe and NVMe-based designs can be tested that minimize time and effort will be presented and analyzed.

This webinar will teach you:

What are the verification pitfalls of PCIe and NVMe protocols.
What are the best practices for verification of layered protocols like PCIe and NVMe.
How to apply metric driven verification techniques to speed up the verification process of PCIe device.
How to identify performance issues during the verification process.
How to maximize reuse of verification components when dealing with new generations of specification.

Go directly to the EE Times Education & Training webcast site to view this presentation. Registration may be required.

Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, verification, PCI Express, PCIe, nonvolatile memory, non-volatile memory, NVM, EE Times Education & Training, Cadence Design Systems,

336/38859 7/25/2012 595 30

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